From: Geoff Berry <gberry@codeaurora.org>
Date: Wed, 27 Sep 2017 17:14:10 +0000 (+0000)
Subject: [AArch64][Falkor] Ignore SP based loads in HW prefetch fixups.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b0ef3feec1be57b043aa6aaaec6c18fba4c8edff;p=llvm

[AArch64][Falkor] Ignore SP based loads in HW prefetch fixups.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38301

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314319 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
index 6df8df0e65a..3acacf7ce58 100644
--- a/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
+++ b/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
@@ -638,9 +638,14 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
     break;
   }
 
+  // Loads from the stack pointer don't get prefetched.
+  unsigned BaseReg = MI.getOperand(BaseRegIdx).getReg();
+  if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
+    return None;
+
   LoadInfo LI;
   LI.DestReg = DestRegIdx == -1 ? 0 : MI.getOperand(DestRegIdx).getReg();
-  LI.BaseReg = MI.getOperand(BaseRegIdx).getReg();
+  LI.BaseReg = BaseReg;
   LI.BaseRegIdx = BaseRegIdx;
   LI.OffsetOpnd = OffsetIdx == -1 ? nullptr : &MI.getOperand(OffsetIdx);
   LI.IsPrePost = IsPrePost;
diff --git a/test/CodeGen/AArch64/falkor-hwpf-fix.mir b/test/CodeGen/AArch64/falkor-hwpf-fix.mir
index 70da36cdb89..38622ae0e49 100644
--- a/test/CodeGen/AArch64/falkor-hwpf-fix.mir
+++ b/test/CodeGen/AArch64/falkor-hwpf-fix.mir
@@ -330,3 +330,26 @@ body: |
   bb.1:
     RET_ReallyLR
 ...
+---
+# Check that we treat sp based loads as non-prefetching.
+
+# CHECK-LABEL: name: hwpf_spbase
+# CHECK-NOT: ORRXrs %xzr
+# CHECK: LDRWui %x15
+# CHECK: LDRWui %sp
+name:            hwpf_spbase
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %w0, %x15
+
+    %w1 = LDRWui %x15, 0 :: ("aarch64-strided-access" load 4)
+    %w17 = LDRWui %sp, 0
+
+    %w0 = SUBWri %w0, 1, 0
+    %wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
+    Bcc 9, %bb.0, implicit %nzcv
+
+  bb.1:
+    RET_ReallyLR
+...