From: Sam Parker Date: Tue, 22 Aug 2017 11:08:21 +0000 (+0000) Subject: [ARM][AArch64] v8.3-A Javascript Conversion X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=abb321130e6fa92495f227ef50fb0074557f9657;p=llvm [ARM][AArch64] v8.3-A Javascript Conversion Armv8.3-A adds instructions that convert a double-precision floating point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance. Differential Revision: https://reviews.llvm.org/D36785 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311448 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index f403f4f6106..d97134356f4 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -522,6 +522,13 @@ let Predicates = [HasV8_3a] in { defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; + // v8.3a floating point conversion for javascript + let Predicates = [HasV8_3a, HasFPARMv8] in + def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, + "fjcvtzs", []> { + let Inst{31} = 0; + } + } // HasV8_3A def : InstAlias<"clrex", (CLREX 0xf)>; diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 5d887c4fcbf..b583f995772 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -1561,6 +1561,15 @@ def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, } } +// v8.3-a Javascript Convert to Signed fixed-point +def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, + (outs SPR:$Sd), (ins DPR:$Dm), + IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm", + []>, + Requires<[HasFPARMv8, HasV8_3a]> { + let Inst{7} = 1; // Z bit +} + // Convert between floating-point and fixed-point // Data type for fixed-point naming convention: // S16 (U=0, sx=0) -> SH diff --git a/test/MC/AArch64/armv8.3a-js.s b/test/MC/AArch64/armv8.3a-js.s new file mode 100644 index 00000000000..23572890338 --- /dev/null +++ b/test/MC/AArch64/armv8.3a-js.s @@ -0,0 +1,10 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-REQ < %t %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fp-armv8 < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NOFP < %t %s + + fjcvtzs w0, d0 +// CHECK: fjcvtzs w0, d0 // encoding: [0x00,0x00,0x7e,0x1e] +// CHECK-REQ: error: instruction requires: armv8.3a +// CHECK-NOFP: error: instruction requires: fp-armv8 diff --git a/test/MC/ARM/armv8.3a-js.s b/test/MC/ARM/armv8.3a-js.s new file mode 100644 index 00000000000..fbbdd981864 --- /dev/null +++ b/test/MC/ARM/armv8.3a-js.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple arm-none-none-eabi -show-encoding -mattr=+v8.3a,+fp-armv8 < %s 2>&1 | FileCheck %s --check-prefix=ARM +// RUN: llvm-mc -triple thumb-none-none-eabi -show-encoding -mattr=+v8.3a,+fp-armv8 < %s 2>&1 | FileCheck %s --check-prefix=THUMB +// RUN: not llvm-mc -triple arm-none-none-eabi -show-encoding -mattr=+v8.2a,+fp-armv8 < %s 2>&1 | FileCheck --check-prefix=REQ-V83 %s +// RUN: not llvm-mc -triple arm-none-none-eabi -show-encoding -mattr=+v8.3a,-fp-armv8 < %s 2>&1 | FileCheck --check-prefix=REQ-FP %s + + vjcvt.s32.f64 s1, d2 +// ARM: vjcvt.s32.f64 s1, d2 @ encoding: [0xc2,0x0b,0xf9,0xee] +// THUMB: vjcvt.s32.f64 s1, d2 @ encoding: [0xf9,0xee,0xc2,0x0b] +// REQ-V83: error: instruction requires: armv8.3a +// REQ-FP: error: instruction requires: FPARMv8 + + vjcvt.s32.f64 s17, d18 +// ARM: vjcvt.s32.f64 s17, d18 @ encoding: [0xe2,0x8b,0xf9,0xee] +// THUMB: vjcvt.s32.f64 s17, d18 @ encoding: [0xf9,0xee,0xe2,0x8b] +// REQ-V83: error: instruction requires: armv8.3a +// REQ-FP: error: instruction requires: FPARMv8 diff --git a/test/MC/Disassembler/AArch64/armv8.3a-js.txt b/test/MC/Disassembler/AArch64/armv8.3a-js.txt new file mode 100644 index 00000000000..a0d40b80584 --- /dev/null +++ b/test/MC/Disassembler/AArch64/armv8.3a-js.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s +# CHECK: fjcvtzs w0, d0 +[0x00,0x00,0x7e,0x1e] diff --git a/test/MC/Disassembler/ARM/armv8.3a-js-arm.txt b/test/MC/Disassembler/ARM/armv8.3a-js-arm.txt new file mode 100644 index 00000000000..e8750036451 --- /dev/null +++ b/test/MC/Disassembler/ARM/armv8.3a-js-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc -triple arm-none-eabi -mattr=+v8.3a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple arm-none-eabi -mattr=+v8.2a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +# RUN: not llvm-mc -triple arm-none-eabi -mattr=+v8.3a,-fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + +[0xc2,0x0b,0xf9,0xee] +# CHECK: vjcvt.s32.f64 s1, d2 +# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding +[0xe2,0x8b,0xf9,0xee] +# CHECK: vjcvt.s32.f64 s17, d18 +# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/armv8.3a-js-thumb.txt b/test/MC/Disassembler/ARM/armv8.3a-js-thumb.txt new file mode 100644 index 00000000000..b21f01232ba --- /dev/null +++ b/test/MC/Disassembler/ARM/armv8.3a-js-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc -triple thumb-none-eabi -mattr=+v8.3a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple thumb-none-eabi -mattr=+v8.2a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +# RUN: not llvm-mc -triple thumb-none-eabi -mattr=+v8.3a,-fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + +[0xf9,0xee,0xc2,0x0b] +# CHECK: vjcvt.s32.f64 s1, d2 +# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding +[0xf9,0xee,0xe2,0x8b] +# CHECK: vjcvt.s32.f64 s17, d18 +# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding