From: Craig Topper <craig.topper@intel.com>
Date: Thu, 20 Jul 2017 06:19:54 +0000 (+0000)
Subject: [X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ab9c5863f30e84caf1d6c0a73005ff85e19cf9b7;p=llvm

[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test.

We should use SHLX and similar instructions for these patterns, but we currently don't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308590 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/shift-bmi2.ll b/test/CodeGen/X86/shift-bmi2.ll
index 51fa880209b..98f9349274a 100644
--- a/test/CodeGen/X86/shift-bmi2.ll
+++ b/test/CodeGen/X86/shift-bmi2.ll
@@ -209,3 +209,96 @@ define i64 @ashr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
   %shl = ashr i64 %x, %shamt
   ret i64 %shl
 }
+
+define i32 @shl32and(i32 %t, i32 %val) nounwind {
+; BMI2-LABEL: shl32and:
+; BMI2:       # BB#0:
+; BMI2-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; BMI2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; BMI2-NEXT:    shll %cl, %eax
+; BMI2-NEXT:    retl
+;
+; BMI264-LABEL: shl32and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shll %cl, %esi
+; BMI264-NEXT:    movl %esi, %eax
+; BMI264-NEXT:    retq
+  %shamt = and i32 %t, 31
+  %res = shl i32 %val, %shamt
+  ret i32 %res
+}
+
+define i64 @shl64and(i64 %t, i64 %val) nounwind {
+; BMI264-LABEL: shl64and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shlq %cl, %rsi
+; BMI264-NEXT:    movq %rsi, %rax
+; BMI264-NEXT:    retq
+  %shamt = and i64 %t, 63
+  %res = shl i64 %val, %shamt
+  ret i64 %res
+}
+
+define i32 @lshr32and(i32 %t, i32 %val) nounwind {
+; BMI2-LABEL: lshr32and:
+; BMI2:       # BB#0:
+; BMI2-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; BMI2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; BMI2-NEXT:    shrl %cl, %eax
+; BMI2-NEXT:    retl
+;
+; BMI264-LABEL: lshr32and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shrl %cl, %esi
+; BMI264-NEXT:    movl %esi, %eax
+; BMI264-NEXT:    retq
+  %shamt = and i32 %t, 31
+  %res = lshr i32 %val, %shamt
+  ret i32 %res
+}
+
+define i64 @lshr64and(i64 %t, i64 %val) nounwind {
+; BMI264-LABEL: lshr64and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shrq %cl, %rsi
+; BMI264-NEXT:    movq %rsi, %rax
+; BMI264-NEXT:    retq
+  %shamt = and i64 %t, 63
+  %res = lshr i64 %val, %shamt
+  ret i64 %res
+}
+
+define i32 @ashr32and(i32 %t, i32 %val) nounwind {
+; BMI2-LABEL: ashr32and:
+; BMI2:       # BB#0:
+; BMI2-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; BMI2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; BMI2-NEXT:    sarl %cl, %eax
+; BMI2-NEXT:    retl
+;
+; BMI264-LABEL: ashr32and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    sarl %cl, %esi
+; BMI264-NEXT:    movl %esi, %eax
+; BMI264-NEXT:    retq
+  %shamt = and i32 %t, 31
+  %res = ashr i32 %val, %shamt
+  ret i32 %res
+}
+
+define i64 @ashr64and(i64 %t, i64 %val) nounwind {
+; BMI264-LABEL: ashr64and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    sarq %cl, %rsi
+; BMI264-NEXT:    movq %rsi, %rax
+; BMI264-NEXT:    retq
+  %shamt = and i64 %t, 63
+  %res = ashr i64 %val, %shamt
+  ret i64 %res
+}