From: Francis Visoiu Mistrih <francisvm@yahoo.com>
Date: Fri, 8 Dec 2017 11:40:06 +0000 (+0000)
Subject: [CodeGen] Move printing MO_CImmediate operands to MachineOperand::print
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ab9bb805758153bd909758e84601c229b2256aeb;p=llvm

[CodeGen] Move printing MO_CImmediate operands to MachineOperand::print

Work towards the unification of MIR and debug output by refactoring the
interfaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320140 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/docs/MIRLangRef.rst b/docs/MIRLangRef.rst
index fff0d3ef0eb..e217b792e62 100644
--- a/docs/MIRLangRef.rst
+++ b/docs/MIRLangRef.rst
@@ -430,7 +430,11 @@ immediate machine operand ``-42``:
 
     %eax = MOV32ri -42
 
-.. TODO: Describe the CIMM (Rare) and FPIMM immediate operands.
+For integers > 64bit, we use a special machine operand, ``MO_CImmediate``,
+which stores the immediate in a ``ConstantInt`` using an ``APInt`` (LLVM's
+arbitrary precision integers).
+
+.. TODO: Describe the FPIMM immediate operands.
 
 .. _register-operands:
 
diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp
index e8a358e5209..b442dab2efb 100644
--- a/lib/CodeGen/MIRPrinter.cpp
+++ b/lib/CodeGen/MIRPrinter.cpp
@@ -854,7 +854,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   const MachineOperand &Op = MI.getOperand(OpIdx);
   printTargetFlags(Op);
   switch (Op.getType()) {
-  case MachineOperand::MO_Register: {
+  case MachineOperand::MO_Register:
+  case MachineOperand::MO_CImmediate: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
@@ -869,9 +870,6 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
     else
       OS << Op.getImm();
     break;
-  case MachineOperand::MO_CImmediate:
-    Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
-    break;
   case MachineOperand::MO_FPImmediate:
     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp
index 85b441c40ab..0cbcb65a99a 100644
--- a/lib/CodeGen/MachineOperand.cpp
+++ b/lib/CodeGen/MachineOperand.cpp
@@ -410,7 +410,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
     OS << getImm();
     break;
   case MachineOperand::MO_CImmediate:
-    getCImm()->getValue().print(OS, false);
+    getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
   case MachineOperand::MO_FPImmediate:
     if (getFPImm()->getType()->isFloatTy()) {
diff --git a/unittests/CodeGen/MachineOperandTest.cpp b/unittests/CodeGen/MachineOperandTest.cpp
index 5926b6767ff..4884d374521 100644
--- a/unittests/CodeGen/MachineOperandTest.cpp
+++ b/unittests/CodeGen/MachineOperandTest.cpp
@@ -9,6 +9,8 @@
 
 #include "llvm/ADT/ilist_node.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/LLVMContext.h"
 #include "llvm/Support/raw_ostream.h"
 #include "gtest/gtest.h"
 
@@ -76,4 +78,26 @@ TEST(MachineOperandTest, PrintSubReg) {
   ASSERT_TRUE(OS.str() == "%physreg1.subreg5");
 }
 
+TEST(MachineOperandTest, PrintCImm) {
+  LLVMContext Context;
+  APInt Int(128, UINT64_MAX);
+  ++Int;
+  ConstantInt *CImm = ConstantInt::get(Context, Int);
+  // Create a MachineOperand with an Imm=(UINT64_MAX + 1)
+  MachineOperand MO = MachineOperand::CreateCImm(CImm);
+
+  // Checking some preconditions on the newly created
+  // MachineOperand.
+  ASSERT_TRUE(MO.isCImm());
+  ASSERT_TRUE(MO.getCImm() == CImm);
+  ASSERT_TRUE(MO.getCImm()->getValue() == Int);
+
+  // Print a MachineOperand containing a SubReg. Here we check that without a
+  // TRI and IntrinsicInfo we can still print the subreg index.
+  std::string str;
+  raw_string_ostream OS(str);
+  MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+  ASSERT_TRUE(OS.str() == "i128 18446744073709551616");
+}
+
 } // end namespace