From: Matt Arsenault Date: Wed, 14 Sep 2016 17:23:48 +0000 (+0000) Subject: AArch64: Use TTI branch functions in branch relaxation X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ab302cda5ec9d003aae385527162371a39c1714c;p=llvm AArch64: Use TTI branch functions in branch relaxation The main change is to return the code size from InsertBranch/RemoveBranch. Patch mostly by Tim Northover git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281505 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 777f2d4a73a..49038fcf9e9 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -525,15 +525,18 @@ public: /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where AnalyzeBranch returns success. It /// returns the number of instructions that were removed. - virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { + /// If \p BytesRemoved is non-null, report the change in code size from the + /// removed instructions. + virtual unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const { llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); } - /// Insert branch code into the end of the specified MachineBasicBlock. - /// The operands to this method are the same as those - /// returned by AnalyzeBranch. This is only invoked in cases where - /// AnalyzeBranch returns success. It returns the number of instructions - /// inserted. + /// Insert branch code into the end of the specified MachineBasicBlock. The + /// operands to this method are the same as those returned by AnalyzeBranch. + /// This is only invoked in cases where AnalyzeBranch returns success. It + /// returns the number of instructions inserted. If \p BytesAdded is non-null, + /// report the change in code size from the added instructions. /// /// It is also invoked by tail merging to add unconditional branches in /// cases where AnalyzeBranch doesn't apply because there was no original @@ -545,10 +548,19 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded = nullptr) const { llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); } + unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, + MachineBasicBlock *DestBB, + const DebugLoc &DL, + int *BytesAdded = nullptr) const { + return InsertBranch(MBB, DestBB, nullptr, + ArrayRef(), DL, BytesAdded); + } + /// Analyze the loop code, return true if it cannot be understoo. Upon /// success, this function returns false and returns information about the /// induction variable and compare instruction used at the end. diff --git a/lib/Target/AArch64/AArch64BranchRelaxation.cpp b/lib/Target/AArch64/AArch64BranchRelaxation.cpp index 92130a1107c..8363823439a 100644 --- a/lib/Target/AArch64/AArch64BranchRelaxation.cpp +++ b/lib/Target/AArch64/AArch64BranchRelaxation.cpp @@ -74,15 +74,6 @@ class AArch64BranchRelaxation : public MachineFunctionPass { void adjustBlockOffsets(MachineBasicBlock &MBB); bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const; - unsigned insertInvertedConditionalBranch(MachineBasicBlock &SrcBB, - MachineBasicBlock::iterator InsPt, - const DebugLoc &DL, - const MachineInstr &OldBr, - MachineBasicBlock &NewDestBB) const; - unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, - MachineBasicBlock &NewDestBB, - const DebugLoc &DL) const; - bool fixupConditionalBranch(MachineInstr &MI); void computeBlockSize(const MachineBasicBlock &MBB); unsigned getInstrOffset(const MachineInstr &MI) const; @@ -130,22 +121,6 @@ void AArch64BranchRelaxation::dumpBBs() { } } -// FIXME: This is a less precise version of MachineBasicBlock::canFallThrough? - -/// \returns true if the specified basic block can fallthrough -/// into the block immediately after it. -static bool hasFallthrough(const MachineBasicBlock &MBB) { - // Get the next machine basic block in the function. - MachineFunction::const_iterator MBBI(MBB); - - // Can't fall off end of function. - auto NextBB = std::next(MBBI); - if (NextBB == MBB.getParent()->end()) - return false; - - return MBB.isSuccessor(&*NextBB); -} - /// scanFunction - Do the initial scan of the function, building up /// information about each block. void AArch64BranchRelaxation::scanFunction() { @@ -228,7 +203,7 @@ AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI) { // Note the new unconditional branch is not being recorded. // There doesn't seem to be meaningful DebugInfo available; this doesn't // correspond to anything in the source. - insertUnconditionalBranch(*OrigBB, *NewBB, DebugLoc()); + TII->insertUnconditionalBranch(*OrigBB, NewBB, DebugLoc()); // Insert an entry into BlockInfo to align it properly with the block numbers. BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); @@ -293,91 +268,18 @@ static MachineBasicBlock *getDestBlock(const MachineInstr &MI) { } } -static unsigned getOppositeConditionOpcode(unsigned Opc) { - switch (Opc) { - default: - llvm_unreachable("unexpected opcode!"); - case AArch64::TBNZW: return AArch64::TBZW; - case AArch64::TBNZX: return AArch64::TBZX; - case AArch64::TBZW: return AArch64::TBNZW; - case AArch64::TBZX: return AArch64::TBNZX; - case AArch64::CBNZW: return AArch64::CBZW; - case AArch64::CBNZX: return AArch64::CBZX; - case AArch64::CBZW: return AArch64::CBNZW; - case AArch64::CBZX: return AArch64::CBNZX; - case AArch64::Bcc: return AArch64::Bcc; // Condition is an operand for Bcc. - } -} - -static inline void invertBccCondition(MachineInstr &MI) { - assert(MI.getOpcode() == AArch64::Bcc && "Unexpected opcode!"); - MachineOperand &CCOp = MI.getOperand(0); - - AArch64CC::CondCode CC = static_cast(CCOp.getImm()); - CCOp.setImm(AArch64CC::getInvertedCondCode(CC)); -} - -/// Insert a conditional branch at the end of \p MBB to \p NewDestBB, using the -/// inverse condition of branch \p OldBr. -/// \returns The number of bytes added to the block. -unsigned AArch64BranchRelaxation::insertInvertedConditionalBranch( - MachineBasicBlock &SrcMBB, - MachineBasicBlock::iterator InsPt, - const DebugLoc &DL, - const MachineInstr &OldBr, - MachineBasicBlock &NewDestBB) const { - unsigned OppositeCondOpc = getOppositeConditionOpcode(OldBr.getOpcode()); - - MachineInstrBuilder MIB = - BuildMI(SrcMBB, InsPt, DL, TII->get(OppositeCondOpc)) - .addOperand(OldBr.getOperand(0)); - - unsigned Opc = OldBr.getOpcode(); - - if (Opc == AArch64::TBZW || Opc == AArch64::TBNZW || - Opc == AArch64::TBZX || Opc == AArch64::TBNZX) - MIB.addOperand(OldBr.getOperand(1)); - - if (OldBr.getOpcode() == AArch64::Bcc) - invertBccCondition(*MIB); - - MIB.addMBB(&NewDestBB); - - return TII->getInstSizeInBytes(*MIB); -} - -/// Insert an unconditional branch at the end of \p MBB to \p DestBB. -/// \returns the number of bytes emitted. -unsigned AArch64BranchRelaxation::insertUnconditionalBranch( - MachineBasicBlock &MBB, - MachineBasicBlock &DestBB, - const DebugLoc &DL) const { - MachineInstr *MI = BuildMI(&MBB, DL, TII->get(AArch64::B)) - .addMBB(&DestBB); - - return TII->getInstSizeInBytes(*MI); -} - -static void changeBranchDestBlock(MachineInstr &MI, - MachineBasicBlock &NewDestBB) { - unsigned OpNum = 0; - unsigned Opc = MI.getOpcode(); - - if (Opc != AArch64::B) { - OpNum = (Opc == AArch64::TBZW || - Opc == AArch64::TBNZW || - Opc == AArch64::TBZX || - Opc == AArch64::TBNZX) ? 2 : 1; - } - - MI.getOperand(OpNum).setMBB(&NewDestBB); -} - /// fixupConditionalBranch - Fix up a conditional branch whose destination is /// too far away to fit in its displacement field. It is converted to an inverse /// conditional branch + an unconditional branch to the destination. bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { - MachineBasicBlock *DestBB = getDestBlock(MI); + DebugLoc DL = MI.getDebugLoc(); + MachineBasicBlock *MBB = MI.getParent(); + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; + SmallVector Cond; + + bool Fail = TII->analyzeBranch(*MBB, TBB, FBB, Cond); + assert(!Fail && "branches to be relaxed must be analyzable"); + (void)Fail; // Add an unconditional branch to the destination and invert the branch // condition to jump over it: @@ -387,80 +289,64 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { // b L1 // L2: - // If the branch is at the end of its MBB and that has a fall-through block, - // direct the updated conditional branch to the fall-through block. Otherwise, - // split the MBB before the next instruction. - MachineBasicBlock *MBB = MI.getParent(); - MachineInstr *BMI = &MBB->back(); - bool NeedSplit = (BMI != &MI) || !hasFallthrough(*MBB); - - if (BMI != &MI) { - if (std::next(MachineBasicBlock::iterator(MI)) == - std::prev(MBB->getLastNonDebugInstr()) && - BMI->isUnconditionalBranch()) { - // Last MI in the BB is an unconditional branch. We can simply invert the - // condition and swap destinations: - // beq L1 - // b L2 - // => - // bne L2 - // b L1 - MachineBasicBlock *NewDest = getDestBlock(*BMI); - if (isBlockInRange(MI, *NewDest)) { - DEBUG(dbgs() << " Invert condition and swap its destination with " - << *BMI); - changeBranchDestBlock(*BMI, *DestBB); - - int NewSize = - insertInvertedConditionalBranch(*MBB, MI.getIterator(), - MI.getDebugLoc(), MI, *NewDest); - int OldSize = TII->getInstSizeInBytes(MI); - BlockInfo[MBB->getNumber()].Size += (NewSize - OldSize); - MI.eraseFromParent(); - return true; - } - } - } + if (FBB && isBlockInRange(MI, *FBB)) { + // Last MI in the BB is an unconditional branch. We can simply invert the + // condition and swap destinations: + // beq L1 + // b L2 + // => + // bne L2 + // b L1 + DEBUG(dbgs() << " Invert condition and swap " + "its destination with " << MBB->back()); + + TII->ReverseBranchCondition(Cond); + int OldSize = 0, NewSize = 0; + TII->RemoveBranch(*MBB, &OldSize); + TII->InsertBranch(*MBB, FBB, TBB, Cond, DL, &NewSize); + + BlockInfo[MBB->getNumber()].Size += (NewSize - OldSize); + return true; + } else if (FBB) { + // We need to split the basic block here to obtain two long-range + // unconditional branches. + auto &NewBB = *MF->CreateMachineBasicBlock(MBB->getBasicBlock()); + MF->insert(++MBB->getIterator(), &NewBB); + + // Insert an entry into BlockInfo to align it properly with the block + // numbers. + BlockInfo.insert(BlockInfo.begin() + NewBB.getNumber(), BasicBlockInfo()); - if (NeedSplit) { - // Analyze the branch so we know how to update the successor lists. - MachineBasicBlock *TBB = nullptr, *FBB = nullptr; - SmallVector Cond; - bool Fail = TII->analyzeBranch(*MBB, TBB, FBB, Cond, false); - assert(!Fail && "branches to relax should be analyzable"); - (void)Fail; - - MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI); - // No need for the branch to the next block. We're adding an unconditional - // branch to the destination. - int delta = TII->getInstSizeInBytes(MBB->back()); - BlockInfo[MBB->getNumber()].Size -= delta; - MBB->back().eraseFromParent(); - // BlockInfo[SplitBB].Offset is wrong temporarily, fixed below + unsigned &NewBBSize = BlockInfo[NewBB.getNumber()].Size; + int NewBrSize; + TII->insertUnconditionalBranch(NewBB, FBB, DL, &NewBrSize); + NewBBSize += NewBrSize; // Update the successor lists according to the transformation to follow. // Do it here since if there's no split, no update is needed. - MBB->replaceSuccessor(FBB, NewBB); - NewBB->addSuccessor(FBB); + MBB->replaceSuccessor(FBB, &NewBB); + NewBB.addSuccessor(FBB); } + // We now have an appropriate fall-through block in place (either naturally or + // just created), so we can invert the condition. MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB)); - DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber() + DEBUG(dbgs() << " Insert B to BB#" << TBB->getNumber() << ", invert condition and change dest. to BB#" << NextBB.getNumber() << '\n'); unsigned &MBBSize = BlockInfo[MBB->getNumber()].Size; // Insert a new conditional branch and a new unconditional branch. - MBBSize += insertInvertedConditionalBranch(*MBB, MBB->end(), - MI.getDebugLoc(), MI, NextBB); - - MBBSize += insertUnconditionalBranch(*MBB, *DestBB, MI.getDebugLoc()); - - // Remove the old conditional branch. It may or may not still be in MBB. - MBBSize -= TII->getInstSizeInBytes(MI); - MI.eraseFromParent(); + int RemovedSize = 0; + TII->ReverseBranchCondition(Cond); + TII->RemoveBranch(*MBB, &RemovedSize); + MBBSize -= RemovedSize; + + int AddedSize = 0; + TII->InsertBranch(*MBB, &NextBB, TBB, Cond, DL, &AddedSize); + MBBSize += AddedSize; // Finally, keep the block offsets up to date. adjustBlockOffsets(*MBB); diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index 39ac480bf85..f6adf8adcba 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -298,7 +298,8 @@ bool AArch64InstrInfo::ReverseBranchCondition( return false; } -unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) return 0; @@ -312,14 +313,23 @@ unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { I = MBB.end(); - if (I == MBB.begin()) + if (I == MBB.begin()) { + if (BytesRemoved) + *BytesRemoved = 4; return 1; + } --I; - if (!isCondBranchOpcode(I->getOpcode())) + if (!isCondBranchOpcode(I->getOpcode())) { + if (BytesRemoved) + *BytesRemoved = 4; return 1; + } // Remove the branch. I->eraseFromParent(); + if (BytesRemoved) + *BytesRemoved = 8; + return 2; } @@ -344,7 +354,8 @@ unsigned AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -353,12 +364,20 @@ unsigned AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB); else instantiateCondBranch(MBB, DL, TBB, Cond); + + if (BytesAdded) + *BytesAdded = 4; + return 1; } // Two-way conditional branch. instantiateCondBranch(MBB, DL, TBB, Cond); BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB); + + if (BytesAdded) + *BytesAdded = 8; + return 2; } diff --git a/lib/Target/AArch64/AArch64InstrInfo.h b/lib/Target/AArch64/AArch64InstrInfo.h index 8960b07227b..dd0f50e4cb7 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.h +++ b/lib/Target/AArch64/AArch64InstrInfo.h @@ -183,10 +183,12 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; bool canInsertSelect(const MachineBasicBlock &, ArrayRef Cond, diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp index 9308dc186d1..3d8889aff8a 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -735,8 +735,10 @@ unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); if (!FBB) { if (Cond.empty()) { @@ -776,8 +778,9 @@ unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB, } } -unsigned -R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); // Note : we leave PRED* instructions there. // They may be needed when predicating instructions. diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h index 2f91520bdfa..f2d306100f4 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.h +++ b/lib/Target/AMDGPU/R600InstrInfo.h @@ -169,9 +169,11 @@ public: unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemvoed = nullptr) const override; bool isPredicated(const MachineInstr &MI) const override; diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 39175a1910d..2bcbac443fb 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1105,17 +1105,23 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, return true; } -unsigned SIInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned SIInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { MachineBasicBlock::iterator I = MBB.getFirstTerminator(); unsigned Count = 0; + unsigned RemovedSize = 0; while (I != MBB.end()) { MachineBasicBlock::iterator Next = std::next(I); + RemovedSize += getInstSizeInBytes(*I); I->eraseFromParent(); ++Count; I = Next; } + if (BytesRemoved) + *BytesRemoved = RemovedSize; + return Count; } @@ -1123,11 +1129,14 @@ unsigned SIInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { if (!FBB && Cond.empty()) { BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) .addMBB(TBB); + if (BytesAdded) + *BytesAdded = 4; return 1; } @@ -1139,6 +1148,9 @@ unsigned SIInstrInfo::InsertBranch(MachineBasicBlock &MBB, if (!FBB) { BuildMI(&MBB, DL, get(Opcode)) .addMBB(TBB); + + if (BytesAdded) + *BytesAdded = 4; return 1; } @@ -1149,6 +1161,9 @@ unsigned SIInstrInfo::InsertBranch(MachineBasicBlock &MBB, BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) .addMBB(FBB); + if (BytesAdded) + *BytesAdded = 8; + return 2; } diff --git a/lib/Target/AMDGPU/SIInstrInfo.h b/lib/Target/AMDGPU/SIInstrInfo.h index e1fd5f19534..d71deee2a0c 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.h +++ b/lib/Target/AMDGPU/SIInstrInfo.h @@ -163,11 +163,13 @@ public: SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool ReverseBranchCondition( SmallVectorImpl &Cond) const override; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index cd215b40d15..6b3b2ea3920 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -382,7 +382,10 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } -unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) return 0; @@ -410,7 +413,9 @@ unsigned ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { + assert(!BytesAdded && "code size not handled"); ARMFunctionInfo *AFI = MBB.getParent()->getInfo(); int BOpc = !AFI->isThumbFunction() ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index cbc4a02bb3c..ad004d0ef9f 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -124,10 +124,12 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/lib/Target/AVR/AVRInstrInfo.cpp b/lib/Target/AVR/AVRInstrInfo.cpp index e2637383d89..943461452aa 100644 --- a/lib/Target/AVR/AVRInstrInfo.cpp +++ b/lib/Target/AVR/AVRInstrInfo.cpp @@ -377,7 +377,10 @@ unsigned AVRInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { + assert(!BytesAdded && "code size not handled"); + // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && @@ -404,7 +407,10 @@ unsigned AVRInstrInfo::InsertBranch(MachineBasicBlock &MBB, return Count; } -unsigned AVRInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned AVRInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; diff --git a/lib/Target/AVR/AVRInstrInfo.h b/lib/Target/AVR/AVRInstrInfo.h index 468bf9aa0e9..f6a3210e28b 100644 --- a/lib/Target/AVR/AVRInstrInfo.h +++ b/lib/Target/AVR/AVRInstrInfo.h @@ -96,8 +96,10 @@ public: bool AllowModify = false) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/lib/Target/BPF/BPFInstrInfo.cpp b/lib/Target/BPF/BPFInstrInfo.cpp index 7aea0512ac7..31f8bfa8c3e 100644 --- a/lib/Target/BPF/BPFInstrInfo.cpp +++ b/lib/Target/BPF/BPFInstrInfo.cpp @@ -134,7 +134,10 @@ unsigned BPFInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { + assert(!BytesAdded && "code size not handled"); + // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -148,7 +151,10 @@ unsigned BPFInstrInfo::InsertBranch(MachineBasicBlock &MBB, llvm_unreachable("Unexpected conditional branch"); } -unsigned BPFInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned BPFInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; diff --git a/lib/Target/BPF/BPFInstrInfo.h b/lib/Target/BPF/BPFInstrInfo.h index cc2e41e4c60..ab8268da350 100644 --- a/lib/Target/BPF/BPFInstrInfo.h +++ b/lib/Target/BPF/BPFInstrInfo.h @@ -49,10 +49,12 @@ public: SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; }; } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index df315c4f5e0..d5da1a9a569 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -537,7 +537,10 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } -unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber()); MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; @@ -561,11 +564,13 @@ unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { unsigned BOpc = Hexagon::J2_jump; unsigned BccOpc = Hexagon::J2_jumpt; assert(validateBranchCond(Cond) && "Invalid branching condition"); assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); // Check if ReverseBranchCondition has asked to reverse this branch // If we want to reverse the branch an odd number of times, we want diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index a0204f73141..158f181b35d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -87,7 +87,8 @@ public: /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where AnalyzeBranch returns success. It /// returns the number of instructions that were removed. - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; /// Insert branch code into the end of the specified MachineBasicBlock. /// The operands to this method are the same as those @@ -101,7 +102,8 @@ public: /// merging needs to be disabled. unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; /// Analyze the loop code, return true if it cannot be understood. Upon /// success, this function returns false and returns information about the diff --git a/lib/Target/Lanai/LanaiInstrInfo.cpp b/lib/Target/Lanai/LanaiInstrInfo.cpp index 673d23daf88..a626da225f1 100644 --- a/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -662,9 +662,11 @@ unsigned LanaiInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef Condition, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TrueBlock && "InsertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); // If condition is empty then an unconditional branch is being inserted. if (Condition.empty()) { @@ -688,7 +690,10 @@ unsigned LanaiInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 2; } -unsigned LanaiInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned LanaiInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator Instruction = MBB.end(); unsigned Count = 0; diff --git a/lib/Target/Lanai/LanaiInstrInfo.h b/lib/Target/Lanai/LanaiInstrInfo.h index 51f6c6ea436..fc845f7ac99 100644 --- a/lib/Target/Lanai/LanaiInstrInfo.h +++ b/lib/Target/Lanai/LanaiInstrInfo.h @@ -86,7 +86,8 @@ public: SmallVectorImpl &Condition, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; // For a comparison instruction, return the source registers in SrcReg and // SrcReg2 if having two register operands, and the value it compares against @@ -135,7 +136,8 @@ public: unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef Condition, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; }; static inline bool isSPLSOpcode(unsigned Opcode) { diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index 4fb82ad613d..12f93fbcac5 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -104,7 +104,10 @@ void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(KillSrc)); } -unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; @@ -264,11 +267,13 @@ unsigned MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && "MSP430 branch conditions have one component!"); + assert(!BytesAdded && "code size not handled"); if (Cond.empty()) { // Unconditional branch? diff --git a/lib/Target/MSP430/MSP430InstrInfo.h b/lib/Target/MSP430/MSP430InstrInfo.h index 1db438c8d67..80f21fd8f9a 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.h +++ b/lib/Target/MSP430/MSP430InstrInfo.h @@ -79,10 +79,12 @@ public: SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; }; } diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 1332258912a..c73698b6b3f 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -117,9 +117,11 @@ unsigned MipsInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); // # of condition operands: // Unconditional branches: 0 @@ -145,7 +147,10 @@ unsigned MipsInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 1; } -unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); unsigned removed; diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 876e9f96c06..de242b84a6a 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -55,11 +55,13 @@ public: SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/lib/Target/NVPTX/NVPTXInstrInfo.cpp index 0c7c6cbc451..9f223130193 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ b/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -205,7 +205,9 @@ bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return true; } -unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin()) return 0; @@ -233,7 +235,10 @@ unsigned NVPTXInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { + assert(!BytesAdded && "code size not handled"); + // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.h b/lib/Target/NVPTX/NVPTXInstrInfo.h index 050bf12fe85..c6bb1b0768a 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -63,10 +63,12 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { return MI.getOperand(2).getImm(); } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index ece7e086575..5a0ed18e0f9 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -605,7 +605,10 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return true; } -unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) return 0; @@ -638,11 +641,13 @@ unsigned PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "PPC branch conditions have two components!"); + assert(!BytesAdded && "code size not handled"); bool isPPC64 = Subtarget.isPPC64(); diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index f7077996aa4..3605fe66336 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -168,10 +168,12 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; // Select analysis. bool canInsertSelect(const MachineBasicBlock &, ArrayRef Cond, diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index bf1de7f1293..61245d21be5 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -244,10 +244,12 @@ unsigned SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && "Sparc branch conditions should have one component!"); + assert(!BytesAdded && "code size not handled"); if (Cond.empty()) { assert(!FBB && "Unconditional branch with multiple successors!"); @@ -269,8 +271,10 @@ unsigned SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 2; } -unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const -{ +unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 8ed97c1479c..432bb32bce8 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -70,11 +70,13 @@ public: SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 4cdc87252c0..9e6d43f239f 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -363,7 +363,10 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return false; } -unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + // Most of the code and comments here are boilerplate. MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; @@ -396,7 +399,8 @@ unsigned SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // In this function we output 32-bit branches, which should always // have enough range. They can be shortened and relaxed by later code // in the pipeline, if desired. @@ -405,6 +409,7 @@ unsigned SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "SystemZ branch conditions have one component!"); + assert(!BytesAdded && "code size not handled"); if (Cond.empty()) { // Unconditional branch? diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h index 0b78a50bf1d..56a0af607b6 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/lib/Target/SystemZ/SystemZInstrInfo.h @@ -164,10 +164,12 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override; bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index 2fd3eab99d7..715940ec60d 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -142,7 +142,10 @@ bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return false; } -unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::instr_iterator I = MBB.instr_end(); unsigned Count = 0; @@ -165,7 +168,10 @@ unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { + assert(!BytesAdded && "code size not handled"); + if (Cond.empty()) { if (!TBB) return 0; diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.h b/lib/Target/WebAssembly/WebAssemblyInstrInfo.h index d93f958ca4c..1f8bc9c5bdb 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.h +++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.h @@ -48,10 +48,12 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; }; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index f25a60509ff..dc2651ef622 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -4441,7 +4441,10 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, return true; } -unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; @@ -4465,11 +4468,13 @@ unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"); + assert(!BytesAdded && "code size not handled"); if (Cond.empty()) { // Unconditional branch? diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 32519c03cf4..02614808c20 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -335,10 +335,12 @@ public: TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool canInsertSelect(const MachineBasicBlock&, ArrayRef Cond, unsigned, unsigned, int&, int&, int&) const override; void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 3981736dc95..083f75e0fc1 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -273,12 +273,14 @@ unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "Unexpected number of components!"); - + assert(!BytesAdded && "code size not handled"); + if (!FBB) { // One way branch. if (Cond.empty()) { // Unconditional branch @@ -302,7 +304,9 @@ unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB, } unsigned -XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) return 0; diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index 783bc6bab5d..c5921583fee 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -57,9 +57,11 @@ public: unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,