From: Jinsong Ji <jji@us.ibm.com>
Date: Tue, 16 Jul 2019 20:24:33 +0000 (+0000)
Subject: [PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtin
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=aae61649ecd608f5205b14e76924cf3b8f155ab0;p=llvm

[PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtin

Summary:
This is exposed by our internal testing.
The reduced testcase will assert with "Impossible reg-to-reg copy"

We can't use COPY to do 32-bit to 64-bit conversion.

Reviewers: kbarton, hfinkel, nemanjai

Reviewed By: hfinkel

Subscribers: hiraditya, MaskRay, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64499

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366255 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCInstrHTM.td b/lib/Target/PowerPC/PPCInstrHTM.td
index 1af65fbb7d3..104b57a70a2 100644
--- a/lib/Target/PowerPC/PPCInstrHTM.td
+++ b/lib/Target/PowerPC/PPCInstrHTM.td
@@ -164,6 +164,8 @@ def : Pat<(int_ppc_tsuspend),
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
-          (RLDICL (i64 (COPY (TABORTWCI 0, (LI 0), 0))), 36, 28)>;
+          (RLDICL (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+                                      (TABORTWCI 0, (LI 0), 0), sub_32)),
+                   36, 28)>;
 
 } // [HasHTM]
diff --git a/test/CodeGen/PowerPC/htm-ttest.ll b/test/CodeGen/PowerPC/htm-ttest.ll
new file mode 100644
index 00000000000..bd9db165f09
--- /dev/null
+++ b/test/CodeGen/PowerPC/htm-ttest.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
+; RUN:     -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
+
+define dso_local void @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    tabortwci. 0, 3, 0
+; CHECK-NEXT:    mfocrf 3, 128
+; CHECK-NEXT:    rldicl 3, 3, 36, 28
+; CHECK-NEXT:    rlwinm. 3, 3, 31, 30, 31
+; CHECK-NEXT:    beqlr+ 0
+; CHECK-NEXT:  # %bb.1:
+  %1 = call i64 @llvm.ppc.ttest() #1
+  %2 = lshr i64 %1, 1
+  %3 = and i64 %2, 3
+  %4 = icmp eq i64 %3, 0
+  br i1 %4, label %5, label %6
+
+5:                                                ; preds = %0
+  ret void
+
+6:                                                ; preds = %0
+  unreachable
+}
+
+; Function Attrs: nounwind
+declare i64 @llvm.ppc.ttest() #1
+