From: Martin Storsjo <martin@martin.st>
Date: Mon, 20 May 2019 19:53:28 +0000 (+0000)
Subject: [AArch64] Handle lowering lround on windows, where long is 32 bit
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a957b3fd1455cc2c5a814e12f4adda0c92403fe0;p=llvm

[AArch64] Handle lowering lround on windows, where long is 32 bit

Differential Revision: https://reviews.llvm.org/D62108

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361192 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index bf6be6761a9..f426da4f1c8 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3083,6 +3083,10 @@ defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
 
+def : Pat<(i32 (lround f32:$Rn)),
+          (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
+def : Pat<(i32 (lround f64:$Rn)),
+          (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>;
 def : Pat<(i64 (lround f32:$Rn)),
           (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
 def : Pat<(i64 (lround f64:$Rn)),
diff --git a/test/CodeGen/AArch64/lround-conv-win.ll b/test/CodeGen/AArch64/lround-conv-win.ll
new file mode 100644
index 00000000000..8bc9213fdce
--- /dev/null
+++ b/test/CodeGen/AArch64/lround-conv-win.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       fcvtas  w8, s0
+; CHECK-NEXT:  sxtw    x0, w8
+; CHECK-NEXT:  ret
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f32(float %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmsws:
+; CHECK:       fcvtas  w0, s0
+; CHECK-NEXT:  ret
+define i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f32(float %x)
+  ret i32 %0
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       fcvtas  w8, d0
+; CHECK-NEXT:  sxtw    x0, w8
+; CHECK-NEXT:  ret
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f64(double %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       fcvtas  w0, d0
+; CHECK-NEXT:  ret
+define i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f64(double %x)
+  ret i32 %0
+}
+
+declare i32 @llvm.lround.i32.f32(float) nounwind readnone
+declare i32 @llvm.lround.i32.f64(double) nounwind readnone