From: Petar Avramovic <Petar.Avramovic@rt-rk.com>
Date: Thu, 5 Sep 2019 11:20:32 +0000 (+0000)
Subject: [MIPS GlobalISel] Select G_FENCE
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a9005fbe93004f9c10a9726398471abcabd1a604;p=llvm

[MIPS GlobalISel] Select G_FENCE

G_FENCE comes form fence instruction. For MIPS fence is generated in
AtomicExpandPass when atomic instruction gets surrounded with fence
instruction when needed.
G_FENCE arguments don't have LLT, because of that there is no job for
legalizer and regbankselect. Instruction select G_FENCE for MIPS32.

Differential Revision: https://reviews.llvm.org/D67181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371056 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsInstructionSelector.cpp b/lib/Target/Mips/MipsInstructionSelector.cpp
index da319265fba..f0c3d3d46bd 100644
--- a/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -752,6 +752,10 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
     I.eraseFromParent();
     return true;
   }
+  case G_FENCE: {
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
+    break;
+  }
   default:
     return false;
   }
diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
new file mode 100644
index 00000000000..5a277be4d91
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @atomic_load_i32(i32* %ptr) { ret void }
+
+...
+---
+name:            atomic_load_i32
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: atomic_load_i32
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load monotonic 4 from %ir.ptr)
+    ; MIPS32: SYNC 0
+    ; MIPS32: $v0 = COPY [[LW]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
+    G_FENCE 4, 1
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir b/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
new file mode 100644
index 00000000000..9e04de27b03
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @atomic_load_i32(i32* %ptr) { ret void }
+
+...
+---
+name:            atomic_load_i32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: atomic_load_i32
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4 from %ir.ptr)
+    ; MIPS32: G_FENCE 4, 1
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
+    G_FENCE 4, 1
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll
new file mode 100644
index 00000000000..ddf55a73534
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i32 @atomic_load_i32(i32* %ptr) {
+; MIPS32-LABEL: atomic_load_i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $2, 0($4)
+; MIPS32-NEXT:    sync
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+  %val = load atomic i32, i32* %ptr acquire, align 4
+  ret i32 %val
+}
diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
new file mode 100644
index 00000000000..de9502123f0
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @atomic_load_i32(i32* %ptr) { ret void }
+
+...
+---
+name:            atomic_load_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: atomic_load_i32
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4 from %ir.ptr)
+    ; MIPS32: G_FENCE 4, 1
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
+    G_FENCE 4, 1
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...