From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 31 May 2019 22:47:36 +0000 (+0000)
Subject: AMDGPU: Fix not adding ImplicitBufferPtr as a live-in
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a8ccb77d84acd4edaed2ba0a4f77780c833ff8e4;p=llvm

AMDGPU: Fix not adding ImplicitBufferPtr as a live-in

Fixes missing test from r293000.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362275 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIFrameLowering.cpp b/lib/Target/AMDGPU/SIFrameLowering.cpp
index e333154f83b..4b2124b14c0 100644
--- a/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -419,7 +419,7 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST,
       }
     }
     MF.getRegInfo().addLiveIn(GitPtrLo);
-    MF.front().addLiveIn(GitPtrLo);
+    MBB.addLiveIn(GitPtrLo);
     BuildMI(MBB, I, DL, SMovB32, RsrcLo)
       .addReg(GitPtrLo)
       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
@@ -487,6 +487,9 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST,
           .addImm(0) // dlc
           .addMemOperand(MMO)
           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
+
+        MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
+        MBB.addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
       }
     } else {
       unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
diff --git a/test/CodeGen/AMDGPU/mesa3d.ll b/test/CodeGen/AMDGPU/mesa3d.ll
new file mode 100644
index 00000000000..4f09b3f7480
--- /dev/null
+++ b/test/CodeGen/AMDGPU/mesa3d.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}scratch_ps:
+; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0{{$}}
+; GCN-DAG: s_mov_b32 s6, -1{{$}}
+; GCN-DAG: s_mov_b32 s7, 0xe8f000
+; GCN-DAG: v_mov_b32_e32 [[V:v[0-9]+]], 2
+; GCN: buffer_store_dword [[V]], off, s[4:7], s2 offset:4
+define amdgpu_ps void @scratch_ps(i32 addrspace(1)* %out, i32 %in) {
+entry:
+  %alloca = alloca i32, addrspace(5)
+  store volatile i32 2, i32 addrspace(5)* %alloca
+  ret void
+}