From: Wangjialin <wangjialin@espressif.com>
Date: Thu, 19 Oct 2017 15:23:01 +0000 (+0800)
Subject: bugfix(i2s): fix bck polarity issue when using pll clock.
X-Git-Tag: v3.1-dev~142^2
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a84db78eb18ebd3cd5d087245b4be5e1f6de53a3;p=esp-idf

bugfix(i2s): fix bck polarity issue when using pll clock.

reported from github: https://github.com/espressif/esp-idf/issues/1119

Digital team think it is due to the decimal divider.
We can reset the i2s tx and rx when calling i2s_stop to avoid this.
---

diff --git a/components/driver/i2s.c b/components/driver/i2s.c
index 2b3b15b3f5..d3d6767a22 100644
--- a/components/driver/i2s.c
+++ b/components/driver/i2s.c
@@ -344,6 +344,7 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
 
     i2s_stop(i2s_num);
 
+
     uint32_t cur_mode = 0;
     if (p_i2s_obj[i2s_num]->channel_num != ch) {
         p_i2s_obj[i2s_num]->channel_num = (ch == 2) ? 2 : 1;
@@ -682,6 +683,11 @@ esp_err_t i2s_stop(i2s_port_t i2s_num)
     I2S[i2s_num]->lc_conf.in_rst = 0;
     I2S[i2s_num]->lc_conf.out_rst = 1;
     I2S[i2s_num]->lc_conf.out_rst = 0;
+
+    I2S[i2s_num]->conf.tx_reset = 1;
+    I2S[i2s_num]->conf.tx_reset = 0;
+    I2S[i2s_num]->conf.rx_reset = 1;
+    I2S[i2s_num]->conf.rx_reset = 0;
     I2S_EXIT_CRITICAL();
     return 0;
 }