From: Oleg Ranevskyy <oranevskyy@accesssoftek.com>
Date: Fri, 18 Nov 2016 21:00:08 +0000 (+0000)
Subject: [ARM] Fix sema check of ARM special register names
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a81947957f74974b97bed04687700000b31b09d9;p=clang

[ARM] Fix sema check of ARM special register names

Summary:
This is a simple sema check patch for arguments of `__builtin_arm_rsr` and the related builtins, which currently do not allow special registers with indexes >7.

Some of the possible register name formats these builtins accept are:
```
{c}p<coprocessor>:<op1>:c<CRn>:c<CRm>:<op2>
```
```
o0:op1:CRn:CRm:op2
```
where `op1` / `op2` are integers in the range [0, 7] and `CRn` / `CRm` are integers in the range [0, 15].

The current sema check does not allow `CRn` > 7 and accepts `op2` up to 15.

Reviewers: LukeCheeseman, rengolin

Subscribers: asl, aemerson, rengolin, cfe-commits

Differential Revision: https://reviews.llvm.org/D26464

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@287378 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Sema/SemaChecking.cpp b/lib/Sema/SemaChecking.cpp
index c1db062f35..3ae540f53b 100644
--- a/lib/Sema/SemaChecking.cpp
+++ b/lib/Sema/SemaChecking.cpp
@@ -4194,7 +4194,7 @@ bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,
 
     SmallVector<int, 5> Ranges;
     if (FiveFields)
-      Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 7, 15, 15});
+      Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
     else
       Ranges.append({15, 7, 15});
 
diff --git a/test/Sema/aarch64-special-register.c b/test/Sema/aarch64-special-register.c
index a4fb92b523..1e658fd907 100644
--- a/test/Sema/aarch64-special-register.c
+++ b/test/Sema/aarch64-special-register.c
@@ -41,7 +41,7 @@ void wsr64_2(unsigned long v) {
 }
 
 unsigned rsr_2() {
-  return __builtin_arm_rsr("0:1:2:3:4");
+  return __builtin_arm_rsr("0:1:15:15:4");
 }
 
 void *rsrp_2() {
@@ -49,7 +49,7 @@ void *rsrp_2() {
 }
 
 unsigned long rsr64_2() {
-  return __builtin_arm_rsr64("0:1:2:3:4");
+  return __builtin_arm_rsr64("0:1:15:15:4");
 }
 
 void wsr_3(unsigned v) {
@@ -68,6 +68,18 @@ unsigned rsr_3() {
   return __builtin_arm_rsr("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
 
+unsigned rsr_4() {
+  return __builtin_arm_rsr("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_5() {
+  return __builtin_arm_rsr("0:8:1:2:3"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_6() {
+  return __builtin_arm_rsr("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
+}
+
 void *rsrp_3() {
   return __builtin_arm_rsrp("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
@@ -75,3 +87,15 @@ void *rsrp_3() {
 unsigned long rsr64_3() {
   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
+
+unsigned long rsr64_4() {
+  return __builtin_arm_rsr64("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_5() {
+  return __builtin_arm_rsr64("0:8:2:3:4"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_6() {
+  return __builtin_arm_rsr64("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
+}
diff --git a/test/Sema/arm-special-register.c b/test/Sema/arm-special-register.c
index 3ded628c13..a9be80fba2 100644
--- a/test/Sema/arm-special-register.c
+++ b/test/Sema/arm-special-register.c
@@ -41,7 +41,7 @@ void wsr64_2(unsigned long v) {
 }
 
 unsigned rsr_2() {
-  return __builtin_arm_rsr("cp0:1:c2:c3:4");
+  return __builtin_arm_rsr("cp0:1:c15:c15:4");
 }
 
 void *rsrp_2() {
@@ -73,13 +73,25 @@ void *rsrp_3() {
 }
 
 unsigned long rsr64_3() {
-  return __builtin_arm_rsr64("cp0:1:c2");
+  return __builtin_arm_rsr64("cp0:1:c15");
 }
 
 unsigned rsr_4() {
   return __builtin_arm_rsr("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
 }
 
+unsigned rsr_5() {
+  return __builtin_arm_rsr("cp0:1:c2:c3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_6() {
+  return __builtin_arm_rsr("cp0:8:c1:c2:3"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_7() {
+  return __builtin_arm_rsr("cp0:1:c16:c16:2"); //expected-error {{invalid special register for builtin}}
+}
+
 void *rsrp_4() {
   return __builtin_arm_rsrp("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
 }
@@ -87,3 +99,11 @@ void *rsrp_4() {
 unsigned long rsr64_4() {
   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
+
+unsigned long rsr64_5() {
+  return __builtin_arm_rsr64("cp0:8:c1"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_6() {
+  return __builtin_arm_rsr64("cp0:1:c16"); //expected-error {{invalid special register for builtin}}
+}