From: Roman Lebedev <lebedev.ri@gmail.com>
Date: Tue, 4 Jun 2019 11:44:50 +0000 (+0000)
Subject: [NFC][Codegen] D62818 - also add tests with X being constant
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a6d7c00a4f2136139cd0662d62c61f5055439c0d;p=llvm

[NFC][Codegen] D62818 - also add tests with X being constant

For X86, these may be a 'BT' pattern, and in general, can cause
the transform to deadlock.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362494 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index 0bc2d8b3776..433904a6fed 100644
--- a/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -301,6 +301,40 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
   ret i1 %res
 }
 
+;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const_eq:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #43605
+; CHECK-NEXT:    movk w8, #43605, lsl #16
+; CHECK-NEXT:    lsr w8, w8, w0
+; CHECK-NEXT:    tst w8, #0x1
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+  %t0 = lshr i32 2857740885, %y
+  %t1 = and i32 %t0, 1
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const2_eq:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w9, #43605
+; CHECK-NEXT:    lsr w8, w8, w0
+; CHECK-NEXT:    movk w9, #43605, lsl #16
+; CHECK-NEXT:    tst w8, w9
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+  %t0 = lshr i32 1, %y
+  %t1 = and i32 %t0, 2857740885
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
diff --git a/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index c76a2e43dae..856f294675e 100644
--- a/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -296,6 +296,40 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
   ret i1 %res
 }
 
+;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const_eq:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #43605
+; CHECK-NEXT:    movk w8, #43605, lsl #16
+; CHECK-NEXT:    lsl w8, w8, w0
+; CHECK-NEXT:    tst w8, #0x1
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+  %t0 = shl i32 2857740885, %y
+  %t1 = and i32 %t0, 1
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const2_eq:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w9, #43605
+; CHECK-NEXT:    lsl w8, w8, w0
+; CHECK-NEXT:    movk w9, #43605, lsl #16
+; CHECK-NEXT:    tst w8, w9
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+  %t0 = shl i32 1, %y
+  %t1 = and i32 %t0, 2857740885
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
diff --git a/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index ff621f6c708..6c30586a959 100644
--- a/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -1119,6 +1119,111 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
   ret i1 %res
 }
 
+;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const_eq:
+; ARM6:       @ %bb.0:
+; ARM6-NEXT:    ldr r1, .LCPI18_0
+; ARM6-NEXT:    mov r2, #1
+; ARM6-NEXT:    bic r0, r2, r1, lsr r0
+; ARM6-NEXT:    bx lr
+; ARM6-NEXT:    .p2align 2
+; ARM6-NEXT:  @ %bb.1:
+; ARM6-NEXT:  .LCPI18_0:
+; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const_eq:
+; ARM78:       @ %bb.0:
+; ARM78-NEXT:    movw r1, #43605
+; ARM78-NEXT:    mov r2, #1
+; ARM78-NEXT:    movt r1, #43605
+; ARM78-NEXT:    bic r0, r2, r1, lsr r0
+; ARM78-NEXT:    bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const_eq:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    ldr r1, .LCPI18_0
+; THUMB6-NEXT:    lsrs r1, r0
+; THUMB6-NEXT:    movs r2, #1
+; THUMB6-NEXT:    ands r2, r1
+; THUMB6-NEXT:    rsbs r0, r2, #0
+; THUMB6-NEXT:    adcs r0, r2
+; THUMB6-NEXT:    bx lr
+; THUMB6-NEXT:    .p2align 2
+; THUMB6-NEXT:  @ %bb.1:
+; THUMB6-NEXT:  .LCPI18_0:
+; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const_eq:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    movw r1, #43605
+; THUMB78-NEXT:    movt r1, #43605
+; THUMB78-NEXT:    lsr.w r0, r1, r0
+; THUMB78-NEXT:    movs r1, #1
+; THUMB78-NEXT:    bic.w r0, r1, r0
+; THUMB78-NEXT:    bx lr
+  %t0 = lshr i32 2857740885, %y
+  %t1 = and i32 %t0, 1
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const2_eq:
+; ARM6:       @ %bb.0:
+; ARM6-NEXT:    ldr r2, .LCPI19_0
+; ARM6-NEXT:    mov r1, #1
+; ARM6-NEXT:    and r0, r2, r1, lsr r0
+; ARM6-NEXT:    clz r0, r0
+; ARM6-NEXT:    lsr r0, r0, #5
+; ARM6-NEXT:    bx lr
+; ARM6-NEXT:    .p2align 2
+; ARM6-NEXT:  @ %bb.1:
+; ARM6-NEXT:  .LCPI19_0:
+; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const2_eq:
+; ARM78:       @ %bb.0:
+; ARM78-NEXT:    movw r1, #43605
+; ARM78-NEXT:    mov r2, #1
+; ARM78-NEXT:    movt r1, #43605
+; ARM78-NEXT:    and r0, r1, r2, lsr r0
+; ARM78-NEXT:    clz r0, r0
+; ARM78-NEXT:    lsr r0, r0, #5
+; ARM78-NEXT:    bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    movs r1, #1
+; THUMB6-NEXT:    lsrs r1, r0
+; THUMB6-NEXT:    ldr r2, .LCPI19_0
+; THUMB6-NEXT:    ands r2, r1
+; THUMB6-NEXT:    rsbs r0, r2, #0
+; THUMB6-NEXT:    adcs r0, r2
+; THUMB6-NEXT:    bx lr
+; THUMB6-NEXT:    .p2align 2
+; THUMB6-NEXT:  @ %bb.1:
+; THUMB6-NEXT:  .LCPI19_0:
+; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    movs r1, #1
+; THUMB78-NEXT:    lsr.w r0, r1, r0
+; THUMB78-NEXT:    movw r1, #43605
+; THUMB78-NEXT:    movt r1, #43605
+; THUMB78-NEXT:    ands r0, r1
+; THUMB78-NEXT:    clz r0, r0
+; THUMB78-NEXT:    lsrs r0, r0, #5
+; THUMB78-NEXT:    bx lr
+  %t0 = lshr i32 1, %y
+  %t1 = and i32 %t0, 2857740885
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
@@ -1154,11 +1259,11 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; THUMB6-NEXT:    ands r2, r0
 ; THUMB6-NEXT:    sxtb r0, r2
 ; THUMB6-NEXT:    cmp r0, #0
-; THUMB6-NEXT:    blt .LBB18_2
+; THUMB6-NEXT:    blt .LBB20_2
 ; THUMB6-NEXT:  @ %bb.1:
 ; THUMB6-NEXT:    movs r0, #0
 ; THUMB6-NEXT:    bx lr
-; THUMB6-NEXT:  .LBB18_2:
+; THUMB6-NEXT:  .LBB20_2:
 ; THUMB6-NEXT:    movs r0, #1
 ; THUMB6-NEXT:    bx lr
 ;
diff --git a/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index 104a43979a0..82572af4d68 100644
--- a/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -1130,6 +1130,111 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
   ret i1 %res
 }
 
+;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const_eq:
+; ARM6:       @ %bb.0:
+; ARM6-NEXT:    ldr r1, .LCPI18_0
+; ARM6-NEXT:    mov r2, #1
+; ARM6-NEXT:    bic r0, r2, r1, lsl r0
+; ARM6-NEXT:    bx lr
+; ARM6-NEXT:    .p2align 2
+; ARM6-NEXT:  @ %bb.1:
+; ARM6-NEXT:  .LCPI18_0:
+; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const_eq:
+; ARM78:       @ %bb.0:
+; ARM78-NEXT:    movw r1, #43605
+; ARM78-NEXT:    mov r2, #1
+; ARM78-NEXT:    movt r1, #43605
+; ARM78-NEXT:    bic r0, r2, r1, lsl r0
+; ARM78-NEXT:    bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const_eq:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    ldr r1, .LCPI18_0
+; THUMB6-NEXT:    lsls r1, r0
+; THUMB6-NEXT:    movs r2, #1
+; THUMB6-NEXT:    ands r2, r1
+; THUMB6-NEXT:    rsbs r0, r2, #0
+; THUMB6-NEXT:    adcs r0, r2
+; THUMB6-NEXT:    bx lr
+; THUMB6-NEXT:    .p2align 2
+; THUMB6-NEXT:  @ %bb.1:
+; THUMB6-NEXT:  .LCPI18_0:
+; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const_eq:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    movw r1, #43605
+; THUMB78-NEXT:    movt r1, #43605
+; THUMB78-NEXT:    lsl.w r0, r1, r0
+; THUMB78-NEXT:    movs r1, #1
+; THUMB78-NEXT:    bic.w r0, r1, r0
+; THUMB78-NEXT:    bx lr
+  %t0 = shl i32 2857740885, %y
+  %t1 = and i32 %t0, 1
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const2_eq:
+; ARM6:       @ %bb.0:
+; ARM6-NEXT:    ldr r2, .LCPI19_0
+; ARM6-NEXT:    mov r1, #1
+; ARM6-NEXT:    and r0, r2, r1, lsl r0
+; ARM6-NEXT:    clz r0, r0
+; ARM6-NEXT:    lsr r0, r0, #5
+; ARM6-NEXT:    bx lr
+; ARM6-NEXT:    .p2align 2
+; ARM6-NEXT:  @ %bb.1:
+; ARM6-NEXT:  .LCPI19_0:
+; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const2_eq:
+; ARM78:       @ %bb.0:
+; ARM78-NEXT:    movw r1, #43605
+; ARM78-NEXT:    mov r2, #1
+; ARM78-NEXT:    movt r1, #43605
+; ARM78-NEXT:    and r0, r1, r2, lsl r0
+; ARM78-NEXT:    clz r0, r0
+; ARM78-NEXT:    lsr r0, r0, #5
+; ARM78-NEXT:    bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    movs r1, #1
+; THUMB6-NEXT:    lsls r1, r0
+; THUMB6-NEXT:    ldr r2, .LCPI19_0
+; THUMB6-NEXT:    ands r2, r1
+; THUMB6-NEXT:    rsbs r0, r2, #0
+; THUMB6-NEXT:    adcs r0, r2
+; THUMB6-NEXT:    bx lr
+; THUMB6-NEXT:    .p2align 2
+; THUMB6-NEXT:  @ %bb.1:
+; THUMB6-NEXT:  .LCPI19_0:
+; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    movs r1, #1
+; THUMB78-NEXT:    lsl.w r0, r1, r0
+; THUMB78-NEXT:    movw r1, #43605
+; THUMB78-NEXT:    movt r1, #43605
+; THUMB78-NEXT:    ands r0, r1
+; THUMB78-NEXT:    clz r0, r0
+; THUMB78-NEXT:    lsrs r0, r0, #5
+; THUMB78-NEXT:    bx lr
+  %t0 = shl i32 1, %y
+  %t1 = and i32 %t0, 2857740885
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
@@ -1165,11 +1270,11 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; THUMB6-NEXT:    ands r2, r0
 ; THUMB6-NEXT:    sxtb r0, r2
 ; THUMB6-NEXT:    cmp r0, #0
-; THUMB6-NEXT:    blt .LBB18_2
+; THUMB6-NEXT:    blt .LBB20_2
 ; THUMB6-NEXT:  @ %bb.1:
 ; THUMB6-NEXT:    movs r0, #0
 ; THUMB6-NEXT:    bx lr
-; THUMB6-NEXT:  .LBB18_2:
+; THUMB6-NEXT:  .LBB20_2:
 ; THUMB6-NEXT:    movs r0, #1
 ; THUMB6-NEXT:    bx lr
 ;
diff --git a/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index b5bf462514e..02ded696861 100644
--- a/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -869,6 +869,91 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
   ret i1 %res
 }
 
+;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; X86-LABEL: scalar_i32_x_is_const_eq:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl $-1437226411, %ecx # imm = 0xAA55AA55
+; X86-NEXT:    btl %eax, %ecx
+; X86-NEXT:    setae %al
+; X86-NEXT:    retl
+;
+; X64-LABEL: scalar_i32_x_is_const_eq:
+; X64:       # %bb.0:
+; X64-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NEXT:    btl %edi, %eax
+; X64-NEXT:    setae %al
+; X64-NEXT:    retq
+  %t0 = lshr i32 2857740885, %y
+  %t1 = and i32 %t0, 1
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; X86-NOBMI-LABEL: scalar_i32_x_is_const2_eq:
+; X86-NOBMI:       # %bb.0:
+; X86-NOBMI-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-NOBMI-NEXT:    movl $1, %eax
+; X86-NOBMI-NEXT:    shrl %cl, %eax
+; X86-NOBMI-NEXT:    testl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-NOBMI-NEXT:    sete %al
+; X86-NOBMI-NEXT:    retl
+;
+; X86-BMI1-LABEL: scalar_i32_x_is_const2_eq:
+; X86-BMI1:       # %bb.0:
+; X86-BMI1-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-BMI1-NEXT:    movl $1, %eax
+; X86-BMI1-NEXT:    shrl %cl, %eax
+; X86-BMI1-NEXT:    testl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-BMI1-NEXT:    sete %al
+; X86-BMI1-NEXT:    retl
+;
+; X86-BMI12-LABEL: scalar_i32_x_is_const2_eq:
+; X86-BMI12:       # %bb.0:
+; X86-BMI12-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-BMI12-NEXT:    movl $1, %ecx
+; X86-BMI12-NEXT:    shrxl %eax, %ecx, %eax
+; X86-BMI12-NEXT:    testl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-BMI12-NEXT:    sete %al
+; X86-BMI12-NEXT:    retl
+;
+; X64-NOBMI-LABEL: scalar_i32_x_is_const2_eq:
+; X64-NOBMI:       # %bb.0:
+; X64-NOBMI-NEXT:    movl %edi, %ecx
+; X64-NOBMI-NEXT:    movl $1, %eax
+; X64-NOBMI-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-NOBMI-NEXT:    shrl %cl, %eax
+; X64-NOBMI-NEXT:    testl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NOBMI-NEXT:    sete %al
+; X64-NOBMI-NEXT:    retq
+;
+; X64-BMI1-LABEL: scalar_i32_x_is_const2_eq:
+; X64-BMI1:       # %bb.0:
+; X64-BMI1-NEXT:    movl %edi, %ecx
+; X64-BMI1-NEXT:    movl $1, %eax
+; X64-BMI1-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-BMI1-NEXT:    shrl %cl, %eax
+; X64-BMI1-NEXT:    testl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI1-NEXT:    sete %al
+; X64-BMI1-NEXT:    retq
+;
+; X64-BMI12-LABEL: scalar_i32_x_is_const2_eq:
+; X64-BMI12:       # %bb.0:
+; X64-BMI12-NEXT:    movl $1, %eax
+; X64-BMI12-NEXT:    shrxl %edi, %eax, %eax
+; X64-BMI12-NEXT:    testl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI12-NEXT:    sete %al
+; X64-BMI12-NEXT:    retq
+  %t0 = lshr i32 1, %y
+  %t1 = and i32 %t0, 2857740885
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
diff --git a/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index 0a6ce5c0e3f..a1b01be7cf6 100644
--- a/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -817,6 +817,91 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
   ret i1 %res
 }
 
+;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; X86-NOBMI-LABEL: scalar_i32_x_is_const_eq:
+; X86-NOBMI:       # %bb.0:
+; X86-NOBMI-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-NOBMI-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-NOBMI-NEXT:    shll %cl, %eax
+; X86-NOBMI-NEXT:    testb $1, %al
+; X86-NOBMI-NEXT:    sete %al
+; X86-NOBMI-NEXT:    retl
+;
+; X86-BMI1-LABEL: scalar_i32_x_is_const_eq:
+; X86-BMI1:       # %bb.0:
+; X86-BMI1-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-BMI1-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-BMI1-NEXT:    shll %cl, %eax
+; X86-BMI1-NEXT:    testb $1, %al
+; X86-BMI1-NEXT:    sete %al
+; X86-BMI1-NEXT:    retl
+;
+; X86-BMI12-LABEL: scalar_i32_x_is_const_eq:
+; X86-BMI12:       # %bb.0:
+; X86-BMI12-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-BMI12-NEXT:    movl $-1437226411, %ecx # imm = 0xAA55AA55
+; X86-BMI12-NEXT:    shlxl %eax, %ecx, %eax
+; X86-BMI12-NEXT:    testb $1, %al
+; X86-BMI12-NEXT:    sete %al
+; X86-BMI12-NEXT:    retl
+;
+; X64-NOBMI-LABEL: scalar_i32_x_is_const_eq:
+; X64-NOBMI:       # %bb.0:
+; X64-NOBMI-NEXT:    movl %edi, %ecx
+; X64-NOBMI-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NOBMI-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-NOBMI-NEXT:    shll %cl, %eax
+; X64-NOBMI-NEXT:    testb $1, %al
+; X64-NOBMI-NEXT:    sete %al
+; X64-NOBMI-NEXT:    retq
+;
+; X64-BMI1-LABEL: scalar_i32_x_is_const_eq:
+; X64-BMI1:       # %bb.0:
+; X64-BMI1-NEXT:    movl %edi, %ecx
+; X64-BMI1-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI1-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-BMI1-NEXT:    shll %cl, %eax
+; X64-BMI1-NEXT:    testb $1, %al
+; X64-BMI1-NEXT:    sete %al
+; X64-BMI1-NEXT:    retq
+;
+; X64-BMI12-LABEL: scalar_i32_x_is_const_eq:
+; X64-BMI12:       # %bb.0:
+; X64-BMI12-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI12-NEXT:    shlxl %edi, %eax, %eax
+; X64-BMI12-NEXT:    testb $1, %al
+; X64-BMI12-NEXT:    sete %al
+; X64-BMI12-NEXT:    retq
+  %t0 = shl i32 2857740885, %y
+  %t1 = and i32 %t0, 1
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; X86-LABEL: scalar_i32_x_is_const2_eq:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl $-1437226411, %ecx # imm = 0xAA55AA55
+; X86-NEXT:    btl %eax, %ecx
+; X86-NEXT:    setae %al
+; X86-NEXT:    retl
+;
+; X64-LABEL: scalar_i32_x_is_const2_eq:
+; X64:       # %bb.0:
+; X64-NEXT:    movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NEXT:    btl %edi, %eax
+; X64-NEXT:    setae %al
+; X64-NEXT:    retq
+  %t0 = shl i32 1, %y
+  %t1 = and i32 %t0, 2857740885
+  %res = icmp eq i32 %t1, 0
+  ret i1 %res
+}
+
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;