From: Simon Pilgrim Date: Wed, 18 Jul 2018 13:01:20 +0000 (+0000) Subject: [X86][SSE] Remove BLENDPD canonicalization from combineTargetShuffle X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a50de627562d232bad68607c635c670795fde55b;p=llvm [X86][SSE] Remove BLENDPD canonicalization from combineTargetShuffle When rL336971 removed the scalar-fp isel patterns, we lost the need for this canonicalization - commutation/folding can handle everything else. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337387 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 7a32ce59d31..37252de7dbc 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -30696,31 +30696,6 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG, } return SDValue(); } - case X86ISD::BLENDI: { - SDValue V0 = N->getOperand(0); - SDValue V1 = N->getOperand(1); - assert(VT == V0.getSimpleValueType() && VT == V1.getSimpleValueType() && - "Unexpected input vector types"); - - // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector - // operands and changing the mask to 1. This saves us a bunch of - // pattern-matching possibilities related to scalar math ops in SSE/AVX. - // x86InstrInfo knows how to commute this back after instruction selection - // if it would help register allocation. - - // TODO: If optimizing for size or a processor that doesn't suffer from - // partial register update stalls, this should be transformed into a MOVSD - // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD. - - if (VT == MVT::v2f64) - if (auto *Mask = dyn_cast(N->getOperand(2))) - if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) { - SDValue NewMask = DAG.getConstant(1, DL, MVT::i8); - return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask); - } - - return SDValue(); - } case X86ISD::MOVSD: case X86ISD::MOVSS: { SDValue V0 = peekThroughBitcasts(N->getOperand(0));