From: Petar Jovanovic Date: Mon, 27 Nov 2017 14:25:36 +0000 (+0000) Subject: [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRC X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a4fca0b4daf86796e16061724a6d71f83a50a645;p=llvm [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRC Make the print format consistent with other assembler instructions. Adding a tab character instead of space in asmstring of Ext and Ins instructions. Removing space around the tab character for JALRC and replacing space with tab in JRC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38144 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319030 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 52bf690a808..b91c9428858 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -369,14 +369,14 @@ class FRxRxRy16_ins f, string asmstr, let rx=0 in class FRR16_JALRC_RA_only_ins nd_, bits<1> l_, string asmstr, InstrItinClass itin>: - FRR16_JALRC ; class FRR16_JALRC_ins nd, bits<1> l, bits<1> ra, string asmstr, InstrItinClass itin>: FRR16_JALRC ; + !strconcat(asmstr, "\t$rx"), [], itin> ; class FRR_SF16_ins _funct, bits<3> _subfunc, @@ -1376,7 +1376,7 @@ def: Mips16Pat<(brind CPU16Regs:$rs), (JrcRx16 CPU16Regs:$rs)> { let isCall=1, hasDelaySlot=0 in def JumpLinkReg16: FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), - "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], II_JALRC> { + "jalrc\t$rs", [(MipsJmpLink CPU16Regs:$rs)], II_JALRC> { let Defs = [RA]; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 4e6d493b91c..e16059d2adc 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1724,7 +1724,7 @@ class ExtBase : InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), - !strconcat(opstr, " $rt, $rs, $pos, $size"), + !strconcat(opstr, "\t$rt, $rs, $pos, $size"), [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT, FrmR, opstr>, ISA_MIPS32R2; @@ -1732,7 +1732,7 @@ class ExtBase: InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src), - !strconcat(opstr, " $rt, $rs, $pos, $size"), + !strconcat(opstr, "\t$rt, $rs, $pos, $size"), [(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size, RO:$src))], II_INS, FrmR, opstr>, ISA_MIPS32R2 { diff --git a/test/CodeGen/Mips/whitespace.ll b/test/CodeGen/Mips/whitespace.ll new file mode 100644 index 00000000000..adb97e1657f --- /dev/null +++ b/test/CodeGen/Mips/whitespace.ll @@ -0,0 +1,62 @@ +; Test that the instructions have the correct whitespace. +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck -strict-whitespace %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -strict-whitespace -check-prefix=32R2 + +@main.L = internal unnamed_addr constant [5 x i8*] [i8* blockaddress(@main, %L1), i8* blockaddress(@main, %L2), i8* blockaddress(@main, %L3), i8* blockaddress(@main, %L4), i8* null], align 4 +@str = private unnamed_addr constant [2 x i8] c"A\00" +@str5 = private unnamed_addr constant [2 x i8] c"B\00" +@str6 = private unnamed_addr constant [2 x i8] c"C\00" +@str7 = private unnamed_addr constant [2 x i8] c"D\00" +@str8 = private unnamed_addr constant [2 x i8] c"E\00" + +define i32 @main() nounwind { +entry: +; 16: jalrc ${{[0-9]+}} +; 16: jrc ${{[0-9]+}} +; 16: jrc $ra + %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str, i32 0, i32 0)) + br label %L1 + +L1: ; preds = %entry, %L3 + %i.0 = phi i32 [ 0, %entry ], [ %inc, %L3 ] + %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str5, i32 0, i32 0)) + br label %L2 + +L2: ; preds = %L1, %L3 + %i.1 = phi i32 [ %i.0, %L1 ], [ %inc, %L3 ] + %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str6, i32 0, i32 0)) + br label %L3 + +L3: ; preds = %L2, %L3 + %i.2 = phi i32 [ %i.1, %L2 ], [ %inc, %L3 ] + %puts7 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str7, i32 0, i32 0)) + %inc = add i32 %i.2, 1 + %arrayidx = getelementptr inbounds [5 x i8*], [5 x i8*]* @main.L, i32 0, i32 %i.2 + %0 = load i8*, i8** %arrayidx, align 4 + indirectbr i8* %0, [label %L1, label %L2, label %L3, label %L4] +L4: ; preds = %L3 + %puts8 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str8, i32 0, i32 0)) + ret i32 0 +} + +declare i32 @puts(i8* nocapture) nounwind + +define i32 @ext(i32 %s, i32 %pos, i32 %sz) nounwind readnone { +entry: +; 32R2: ext ${{[0-9]+}}, $4, 5, 9 + %shr = lshr i32 %s, 5 + %and = and i32 %shr, 511 + ret i32 %and +} + +define void @ins(i32 %s, i32* nocapture %d) nounwind { +entry: +; 32R2: ins ${{[0-9]+}}, $4, 5, 9 + %and = shl i32 %s, 5 + %shl = and i32 %and, 16352 + %tmp3 = load i32, i32* %d, align 4 + %and5 = and i32 %tmp3, -16353 + %or = or i32 %and5, %shl + store i32 %or, i32* %d, align 4 + ret void +}