From: Craig Topper <craig.topper@gmail.com>
Date: Fri, 27 May 2016 06:59:39 +0000 (+0000)
Subject: [AVX512][Builtin] Fix palignr intrinsic for avx512vlbw. The immediate should not... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a48aeaa5c8304e27e8205326a4c38a893e98fefc;p=clang

[AVX512][Builtin] Fix palignr intrinsic for avx512vlbw. The immediate should not be multiplied by 8.

The 512-bit version was fixed recently but this was missed.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@270970 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Headers/avx512vlbwintrin.h b/lib/Headers/avx512vlbwintrin.h
index d35dc7e3bf..71dac6b3bb 100644
--- a/lib/Headers/avx512vlbwintrin.h
+++ b/lib/Headers/avx512vlbwintrin.h
@@ -3338,25 +3338,25 @@ _mm256_mask_permutexvar_epi16 (__m256i __W, __mmask16 __M, __m256i __A,
 
 #define _mm_mask_alignr_epi8(W, U, A, B, N) __extension__ ({ \
   (__m128i)__builtin_ia32_palignr128_mask((__v16qi)(__m128i)(A), \
-                                          (__v16qi)(__m128i)(B), (int)(N) * 8, \
+                                          (__v16qi)(__m128i)(B), (int)(N), \
                                           (__v16qi)(__m128i)(W), \
                                           (__mmask16)(U)); })
 
 #define _mm_maskz_alignr_epi8(U, A, B, N) __extension__ ({ \
   (__m128i)__builtin_ia32_palignr128_mask((__v16qi)(__m128i)(A), \
-                                          (__v16qi)(__m128i)(B), (int)(N) * 8, \
+                                          (__v16qi)(__m128i)(B), (int)(N), \
                                           (__v16qi)_mm_setzero_si128(), \
                                           (__mmask16)(U)); })
 
 #define _mm256_mask_alignr_epi8(W, U, A, B, N) __extension__ ({ \
   (__m256i)__builtin_ia32_palignr256_mask((__v32qi)(__m256i)(A), \
-                                          (__v32qi)(__m256i)(B), (int)(N) * 8, \
+                                          (__v32qi)(__m256i)(B), (int)(N), \
                                           (__v32qi)(__m256i)(W), \
                                           (__mmask32)(U)); })
 
 #define _mm256_maskz_alignr_epi8(U, A, B, N) __extension__ ({ \
   (__m256i)__builtin_ia32_palignr256_mask((__v32qi)(__m256i)(A), \
-                                          (__v32qi)(__m256i)(B), (int)(N) * 8, \
+                                          (__v32qi)(__m256i)(B), (int)(N), \
                                           (__v32qi)_mm256_setzero_si256(), \
                                           (__mmask32)(U)); })