From: Martin Bohme <mboehme@google.com>
Date: Tue, 24 Jan 2017 12:31:30 +0000 (+0000)
Subject: [X86][SSE] Add explicit braces to avoid -Wdangling-else warning.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a441aef21cb66b22f99f0cf2175aa2d0bf930cc3;p=llvm

[X86][SSE] Add explicit braces to avoid -Wdangling-else warning.

Reviewers: RKSimon

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D29076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292924 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 615ab9eb0c9..c6ef240b9b1 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -30478,11 +30478,12 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
   // Out of range logical bit shifts are guaranteed to be zero.
   // Out of range arithmetic bit shifts splat the sign bit.
   APInt ShiftVal = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
-  if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt))
+  if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt)) {
     if (LogicalShift)
       return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N));
     else
       ShiftVal = NumBitsPerElt - 1;
+  }
 
   SDValue N0 = N->getOperand(0);