From: Craig Topper <craig.topper@intel.com>
Date: Mon, 28 Aug 2017 18:44:28 +0000 (+0000)
Subject: [InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the NSW flag... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a3ced95cbe8b893084911560408de4987a4658e6;p=llvm

[InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the NSW flag when handling Add in SimplifyDemandedUseBits.

This is a typo from r311789.

This should fix PR34349.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311902 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 39d1dfe27a0..cda2ce6c91c 100644
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -426,7 +426,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
       return I->getOperand(1);
 
     // Otherwise just compute the known bits of the result.
-    bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoUnsignedWrap();
+    bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
     Known = KnownBits::computeForAddSub(I->getOpcode() == Instruction::Add,
                                         NSW, LHSKnown, RHSKnown);
     break;
diff --git a/test/Transforms/InstCombine/pr34349.ll b/test/Transforms/InstCombine/pr34349.ll
new file mode 100644
index 00000000000..b88f77a4c86
--- /dev/null
+++ b/test/Transforms/InstCombine/pr34349.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+;RUN: opt -instcombine -S %s | FileCheck %s
+
+define i8 @fast_div_201(i8 %p) {
+; CHECK-LABEL: @fast_div_201(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V3:%.*]] = zext i8 [[P:%.*]] to i16
+; CHECK-NEXT:    [[V4:%.*]] = mul nuw nsw i16 [[V3]], 71
+; CHECK-NEXT:    [[V5:%.*]] = lshr i16 [[V4]], 8
+; CHECK-NEXT:    [[V6:%.*]] = trunc i16 [[V5]] to i8
+; CHECK-NEXT:    [[V7:%.*]] = sub i8 [[P]], [[V6]]
+; CHECK-NEXT:    [[V8:%.*]] = lshr i8 [[V7]], 1
+; CHECK-NEXT:    [[V13:%.*]] = add nuw i8 [[V8]], [[V6]]
+; CHECK-NEXT:    [[V14:%.*]] = lshr i8 [[V13]], 7
+; CHECK-NEXT:    ret i8 [[V14]]
+;
+entry:
+  %v3 = zext i8 %p to i16
+  %v4 = mul i16 %v3, 71
+  %v5 = lshr i16 %v4, 8
+  %v6 = trunc i16 %v5 to i8
+  %v7 = sub i8 %p, %v6
+  %v8 = lshr i8 %v7, 1
+  %v13 = add i8 %v6, %v8
+  %v14 = lshr i8 %v13, 7
+  ret i8 %v14
+}