From: Simon Pilgrim Date: Tue, 5 Mar 2019 13:52:09 +0000 (+0000) Subject: [X86] Add test cases for D58874 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=a38100a64a0548ec817b48e4fe0a7f599e32d779;p=llvm [X86] Add test cases for D58874 Add scalar and vector test cases for missing (add (add (xor a, -1), b), 1) -> (sub b, a) fold git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355400 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/combine-add.ll b/test/CodeGen/X86/combine-add.ll index 8eb4a5d76b6..212f4aaefee 100644 --- a/test/CodeGen/X86/combine-add.ll +++ b/test/CodeGen/X86/combine-add.ll @@ -349,3 +349,48 @@ define <4 x i32> @combine_vec_add_sextinreg(<4 x i32> %a0, <4 x i32> %a1) { %3 = add <4 x i32> %2, %a1 ret <4 x i32> %3 } + +; TODO: (add (add (xor a, -1), b), 1) -> (sub b, a) +define i32 @combine_add_add_not(i32 %a, i32 %b) { +; SSE-LABEL: combine_add_add_not: +; SSE: # %bb.0: +; SSE-NEXT: # kill: def $esi killed $esi def $rsi +; SSE-NEXT: # kill: def $edi killed $edi def $rdi +; SSE-NEXT: notl %edi +; SSE-NEXT: leal 1(%rdi,%rsi), %eax +; SSE-NEXT: retq +; +; AVX-LABEL: combine_add_add_not: +; AVX: # %bb.0: +; AVX-NEXT: # kill: def $esi killed $esi def $rsi +; AVX-NEXT: # kill: def $edi killed $edi def $rdi +; AVX-NEXT: notl %edi +; AVX-NEXT: leal 1(%rdi,%rsi), %eax +; AVX-NEXT: retq + %nota = xor i32 %a, -1 + %add = add i32 %nota, %b + %r = add i32 %add, 1 + ret i32 %r +} + +define <4 x i32> @combine_vec_add_add_not(<4 x i32> %a, <4 x i32> %b) { +; SSE-LABEL: combine_vec_add_add_not: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: paddd %xmm1, %xmm0 +; SSE-NEXT: paddd {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_add_add_not: +; AVX: # %bb.0: +; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq + %nota = xor <4 x i32> %a, + %add = add <4 x i32> %nota, %b + %r = add <4 x i32> %add, + ret <4 x i32> %r +}