From: Craig Topper <craig.topper@intel.com>
Date: Mon, 19 Aug 2019 04:08:44 +0000 (+0000)
Subject: [X86] Fix the lower1BitShuffle code added in r369215 to correctly pass the widened... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=9d995c15911c4d1ec0ab4db3abee7e5685beefe1;p=llvm

[X86] Fix the lower1BitShuffle code added in r369215 to correctly pass the widened vector to the KSHIFT node.

Not sure how to test this as we have tests that exercise this code,
but nothing failed for the types not matching. Since all the k-registers
use equivalent register classes everything just ends up working.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369228 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 03181a625b8..ae3aed0055a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -16654,7 +16654,7 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
         SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
                                   DAG.getUNDEF(WideVT), V,
                                   DAG.getIntPtrConstant(0, DL));
-        Res = DAG.getNode(Opcode, DL, WideVT, V,
+        Res = DAG.getNode(Opcode, DL, WideVT, Res,
                           DAG.getConstant(ShiftAmt, DL, MVT::i8));
         return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
                            DAG.getIntPtrConstant(0, DL));