From: John Baldwin <jhb@FreeBSD.org>
Date: Fri, 11 Aug 2017 18:35:19 +0000 (+0000)
Subject: [mips] clang-format MipsSubtarget.cpp.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=9c0367e30fe28a291bb0c4fbbc2f5743e587d6af;p=llvm

[mips] clang-format MipsSubtarget.cpp.

This only fixes a few things and serves as my initial test commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310742 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index eba21e0a1c6..e160eac30d8 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -57,7 +57,7 @@ static cl::opt<bool>
     GPOpt("mgpopt", cl::Hidden,
           cl::desc("Enable gp-relative addressing of mips small data items"));
 
-void MipsSubtarget::anchor() { }
+void MipsSubtarget::anchor() {}
 
 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              bool little, const MipsTargetMachine &TM)
@@ -136,8 +136,8 @@ bool MipsSubtarget::enablePostRAScheduler() const { return true; }
 
 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
   CriticalPathRCs.clear();
-  CriticalPathRCs.push_back(isGP64bit() ?
-                            &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+  CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
+                                        : &Mips::GPR32RegClass);
 }
 
 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {