From: Mikhail Maltsev <mikhail.maltsev@arm.com>
Date: Mon, 8 Jul 2019 09:44:52 +0000 (+0000)
Subject: [ARM] Relax constraints on operands of VQxDMLxDH instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=9ad700079eb076a4831a8afd0d7b8556f76581d7;p=llvm

[ARM] Relax constraints on operands of VQxDMLxDH instructions

Summary:
According to a recently updated Armv8-M spec
(https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf) the
32-bit width versions of the following instructions:
* VQDMLADH
* VQDMLADHX
* VQRDMLADH
* VQRDMLADHX
* VQDMLSDH
* VQDMLSDHX
* VQRDMLSDH
* VQRDMLSDHX
are no longer unpredictable when their output register is the same as
one of the input registers.

This patch updates the assembler parser and the corresponding tests
and also removes @earlyclobber from the instruction constraints.

Reviewers: simon_tatham, ostannard, dmgreen, SjoerdMeijer, samparker

Reviewed By: simon_tatham

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64250

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365306 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td
index e1882635c8b..06f8b18320c 100644
--- a/lib/Target/ARM/ARMInstrMVE.td
+++ b/lib/Target/ARM/ARMInstrMVE.td
@@ -2834,13 +2834,10 @@ class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
 }
 
 class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
-                    string suffix, bits<2> size, bit earlyclobber,
-                    list<dag> pattern=[]>
+                    string suffix, bits<2> size, list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
                    (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
-                   vpred_n,
-                   !if(earlyclobber, "@earlyclobber $Qd,", "") # "$Qd = $Qd_src",
-                   pattern> {
+                   vpred_n, "$Qd = $Qd_src", pattern> {
   bits<4> Qn;
 
   let Inst{28} = subtract;
@@ -2855,9 +2852,9 @@ class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
 
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
                                bit round, bit subtract> {
-  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00, 0b0>;
-  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01, 0b0>;
-  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10, 0b1>;
+  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00>;
+  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
+  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10>;
 }
 
 defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 3ff3af9dd58..1da9452f1d2 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -7865,15 +7865,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
   case ARM::MVE_VMULLs32bh:
   case ARM::MVE_VMULLs32th:
   case ARM::MVE_VMULLu32bh:
-  case ARM::MVE_VMULLu32th:
-  case ARM::MVE_VQDMLADHs32:
-  case ARM::MVE_VQDMLADHXs32:
-  case ARM::MVE_VQRDMLADHs32:
-  case ARM::MVE_VQRDMLADHXs32:
-  case ARM::MVE_VQDMLSDHs32:
-  case ARM::MVE_VQDMLSDHXs32:
-  case ARM::MVE_VQRDMLSDHs32:
-  case ARM::MVE_VQRDMLSDHXs32: {
+  case ARM::MVE_VMULLu32th: {
     if (Operands[3]->getReg() == Operands[4]->getReg()) {
       return Error (Operands[3]->getStartLoc(),
                     "Qd register and Qn register can't be identical");
diff --git a/test/MC/ARM/mve-qdest-qsrc.s b/test/MC/ARM/mve-qdest-qsrc.s
index 851ca12d29d..410c69122bd 100644
--- a/test/MC/ARM/mve-qdest-qsrc.s
+++ b/test/MC/ARM/mve-qdest-qsrc.s
@@ -60,10 +60,12 @@ vqrdmladhx.s16 q0, q0, q1
 # CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
 vqrdmladhx.s32 q1, q0, q4
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+# CHECK: vqrdmladhx.s32 q1, q1, q0  @ encoding: [0x22,0xee,0x01,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q1, q0  @ encoding: [0x22,0xee,0x01,0x3e]
 vqrdmladhx.s32 q1, q1, q0
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+# CHECK: vqrdmladhx.s32 q1, q0, q1  @ encoding: [0x20,0xee,0x03,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q0, q1  @ encoding: [0x20,0xee,0x03,0x3e]
 vqrdmladhx.s32 q1, q0, q1
 
 # CHECK: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
@@ -126,10 +128,12 @@ vqrdmlsdh.s16 q0, q7, q4
 # CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
 vqrdmlsdh.s32 q0, q6, q7
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+# CHECK: vqrdmlsdh.s32 q0, q0, q7  @ encoding: [0x20,0xfe,0x0f,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q0, q7  @ encoding: [0x20,0xfe,0x0f,0x0e]
 vqrdmlsdh.s32 q0, q0, q7
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+# CHECK: vqrdmlsdh.s32 q0, q6, q0  @ encoding: [0x2c,0xfe,0x01,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q0  @ encoding: [0x2c,0xfe,0x01,0x0e]
 vqrdmlsdh.s32 q0, q6, q0
 
 # CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]