From: Simon Dardis Date: Fri, 11 Aug 2017 14:36:05 +0000 (+0000) Subject: [mips] Lift the assertion on the types that can be used with MipsGPRel X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=9ac295da5f10f680a3d9f931d9c5ff6ab141e582;p=llvm [mips] Lift the assertion on the types that can be used with MipsGPRel Post commit review of rL308619 highlighted the need for handling N64 with -fno-pic. Testing reveale a stale assert when generating a GP relative addressing mode. This patch removes that assert and adds the necessary patterns for MIPS64 to perform gp relative addressing with -fno-pic (and the implicit -mno-abicalls + -mgpopt). Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D36472 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310713 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 3dba7ce30ca..ecf8f5f864f 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -610,6 +610,12 @@ multiclass MipsHighestHigherHiLoRelocs { let AdditionalPredicates = [NotInMicroMips] in defm : MipsHighestHigherHiLoRelocs, SYM_64; +// gp_rel relocs +def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)), + (DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64; +def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)), + (DADDiu GPR64:$gp, tconstpool:$in)>, ABI_N64; + def : WrapperPat; def : WrapperPat; def : WrapperPat; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 7be84c14eef..4c8f87f9381 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -2057,7 +2057,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, const GlobalObject *GO = GV->getBaseObject(); if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) // %gp_rel relocation - return getAddrGPRel(N, SDLoc(N), Ty, DAG); + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); // %hi/%lo relocation return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) @@ -2212,7 +2212,7 @@ lowerConstantPool(SDValue Op, SelectionDAG &DAG) const if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), getTargetMachine())) // %gp_rel relocation - return getAddrGPRel(N, SDLoc(N), Ty, DAG); + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 21b038e579f..4933cc1eb21 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -475,13 +475,12 @@ class TargetRegisterClass; // (add $gp, %gp_rel(sym)) template SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, - SelectionDAG &DAG) const { - assert(Ty == MVT::i32); + SelectionDAG &DAG, bool IsN64) const { SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); - return DAG.getNode(ISD::ADD, DL, Ty, - DAG.getRegister(Mips::GP, Ty), - DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), - GPRel)); + return DAG.getNode( + ISD::ADD, DL, Ty, + DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty), + DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel)); } /// This function fills Ops, which is the list of operands that will later diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 89a5854bede..12a84b10586 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -220,6 +220,8 @@ def IsSym32 : Predicate<"Subtarget->HasSym32()">, AssemblerPredicate<"FeatureSym32">; def IsSym64 : Predicate<"!Subtarget->HasSym32()">, AssemblerPredicate<"!FeatureSym32">; +def IsN64 : Predicate<"Subtarget->isABI_N64()">; +def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">; def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; def RelocPIC : Predicate<"TM.isPositionIndependent()">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; @@ -401,6 +403,16 @@ class MADD4 { list AdditionalPredicates = [HasMadd4]; } +// Classses used for separating expansions that differ based on the ABI in +// use. +class ABI_N64 { + list AdditionalPredicates = [IsN64]; +} + +class ABI_NOT_N64 { + list AdditionalPredicates = [IsNotN64]; +} + //===----------------------------------------------------------------------===// class MipsPat : Pat, PredicateControl { @@ -2748,9 +2760,9 @@ def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>; // gp_rel relocs def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), - (ADDiu GPR32:$gp, tglobaladdr:$in)>; + (ADDiu GPR32:$gp, tglobaladdr:$in)>, ABI_NOT_N64; def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), - (ADDiu GPR32:$gp, tconstpool:$in)>; + (ADDiu GPR32:$gp, tconstpool:$in)>, ABI_NOT_N64; // wrapper_pic class WrapperPat: diff --git a/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/test/CodeGen/Mips/2008-07-15-SmallSection.ll index 21495423200..3f42489141f 100644 --- a/test/CodeGen/Mips/2008-07-15-SmallSection.ll +++ b/test/CodeGen/Mips/2008-07-15-SmallSection.ll @@ -1,14 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \ +; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \ ; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt \ -; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON -; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32 +; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \ ; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -membedded-data \ -; RUN: | FileCheck %s --check-prefixes=EMBDATA,COMMON +; RUN: | FileCheck %s --check-prefixes=EMBDATA,COMMON,ADDR32 + +; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n64 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls,+sym32 -mgpopt -target-abi n64 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n32 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32 ; Test the layout of objects when compiling for static, noabicalls environment. %struct.anon = type { i32, i32 } +; Check that when synthesizing a pointer to the second element of foo, that +; we use the correct addition operation. O32 and N32 have 32-bit address +; spaces, so they use addiu. N64 has a 64bit address space, but has a submode +; where symbol sizes are 32 bits. In those cases we use daddiu. + +; CHECK-LABEL: A1: +; N64: daddiu ${{[0-9]+}}, $gp, %gp_rel(foo) +; ADDR32: addiu ${{[0-9]+}}, $gp, %gp_rel(foo) + ; BASIC: .type s0,@object ; BASIC-NEXT: .section .sdata,"aw",@progbits