From: Jiang Jiang Jian <jack@espressif.com>
Date: Tue, 15 May 2018 01:49:56 +0000 (+0800)
Subject: Merge branch 'bugfix/rename_clk_rst_bits_for_spi' into 'master'
X-Git-Tag: v3.1-beta1~154
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=97a228e6abf1d7a75f696c1e40098a5e1c670d52;p=esp-idf

Merge branch 'bugfix/rename_clk_rst_bits_for_spi' into 'master'

rename clock enable and reset bits for SPI modules

See merge request idf/esp-idf!2293
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97a228e6abf1d7a75f696c1e40098a5e1c670d52