From: Matt Arsenault Date: Wed, 21 Oct 2015 22:37:51 +0000 (+0000) Subject: AMDGPU: Fix adding redundant m0 uses X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=96d418302ea0f783b94683df357bad50d56fe838;p=llvm AMDGPU: Fix adding redundant m0 uses BuildMI already adds these since they are defined correctly now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250961 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/SILowerControlFlow.cpp b/lib/Target/AMDGPU/SILowerControlFlow.cpp index 72ed1956d73..126f6245dfc 100644 --- a/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -438,7 +438,6 @@ void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) { MachineInstr *MovRel = BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst) .addReg(Reg) - .addReg(AMDGPU::M0, RegState::Implicit) .addReg(Vec, RegState::Implicit); LoadM0(MI, MovRel, Off); @@ -460,7 +459,6 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32)) .addReg(Reg, RegState::Define) .addReg(Val) - .addReg(AMDGPU::M0, RegState::Implicit) .addReg(Dst, RegState::Implicit); LoadM0(MI, MovRel, Off);