From: David Green <david.green@arm.com>
Date: Tue, 1 Oct 2019 18:04:02 +0000 (+0000)
Subject: [ARM] Some MVE shuffle plus extend tests. NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=92d26cbe33371f09c3472238d096c4e870828fa8;p=llvm

[ARM] Some MVE shuffle plus extend tests. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373368 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/Thumb2/mve-shuffleext.ll b/test/CodeGen/Thumb2/mve-shuffleext.ll
new file mode 100644
index 00000000000..d8b94a4a850
--- /dev/null
+++ b/test/CodeGen/Thumb2/mve-shuffleext.ll
@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
+
+define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src) {
+; CHECK-LABEL: sext_0246:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u16 r0, q0[0]
+; CHECK-NEXT:    vmov.32 q1[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-NEXT:    vmov.32 q1[1], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[4]
+; CHECK-NEXT:    vmov.32 q1[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[6]
+; CHECK-NEXT:    vmov.32 q1[3], r0
+; CHECK-NEXT:    vmovlb.s16 q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %out = sext <4 x i16> %strided.vec to <4 x i32>
+  ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src) {
+; CHECK-LABEL: sext_1357:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev32.16 q0, q0
+; CHECK-NEXT:    vmovlb.s16 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %out = sext <4 x i16> %strided.vec to <4 x i32>
+  ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @zext_0246(<8 x i16> %src) {
+; CHECK-LABEL: zext_0246:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u16 r0, q0[0]
+; CHECK-NEXT:    vmov.32 q1[0], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-NEXT:    vmov.32 q1[1], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[4]
+; CHECK-NEXT:    vmov.32 q1[2], r0
+; CHECK-NEXT:    vmov.u16 r0, q0[6]
+; CHECK-NEXT:    vmov.32 q1[3], r0
+; CHECK-NEXT:    vmovlb.u16 q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %out = zext <4 x i16> %strided.vec to <4 x i32>
+  ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src) {
+; CHECK-LABEL: zext_1357:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev32.16 q0, q0
+; CHECK-NEXT:    vmovlb.u16 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %out = zext <4 x i16> %strided.vec to <4 x i32>
+  ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @sext_02468101214(<16 x i8> %src) {
+; CHECK-LABEL: sext_02468101214:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u8 r0, q0[0]
+; CHECK-NEXT:    vmov.16 q1[0], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[2]
+; CHECK-NEXT:    vmov.16 q1[1], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[4]
+; CHECK-NEXT:    vmov.16 q1[2], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[6]
+; CHECK-NEXT:    vmov.16 q1[3], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[8]
+; CHECK-NEXT:    vmov.16 q1[4], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[10]
+; CHECK-NEXT:    vmov.16 q1[5], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[12]
+; CHECK-NEXT:    vmov.16 q1[6], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[14]
+; CHECK-NEXT:    vmov.16 q1[7], r0
+; CHECK-NEXT:    vmovlb.s8 q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  %out = sext <8 x i8> %strided.vec to <8 x i16>
+  ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src) {
+; CHECK-LABEL: sext_13579111315:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev16.8 q0, q0
+; CHECK-NEXT:    vmovlb.s8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+  %out = sext <8 x i8> %strided.vec to <8 x i16>
+  ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @zext_02468101214(<16 x i8> %src) {
+; CHECK-LABEL: zext_02468101214:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.u8 r0, q0[0]
+; CHECK-NEXT:    vmov.16 q1[0], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[2]
+; CHECK-NEXT:    vmov.16 q1[1], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[4]
+; CHECK-NEXT:    vmov.16 q1[2], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[6]
+; CHECK-NEXT:    vmov.16 q1[3], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[8]
+; CHECK-NEXT:    vmov.16 q1[4], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[10]
+; CHECK-NEXT:    vmov.16 q1[5], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[12]
+; CHECK-NEXT:    vmov.16 q1[6], r0
+; CHECK-NEXT:    vmov.u8 r0, q0[14]
+; CHECK-NEXT:    vmov.16 q1[7], r0
+; CHECK-NEXT:    vmovlb.u8 q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  %out = zext <8 x i8> %strided.vec to <8 x i16>
+  ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src) {
+; CHECK-LABEL: zext_13579111315:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev16.8 q0, q0
+; CHECK-NEXT:    vmovlb.u8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+  %out = zext <8 x i8> %strided.vec to <8 x i16>
+  ret <8 x i16> %out
+}