From: Matt Arsenault Date: Mon, 8 Jul 2019 16:53:53 +0000 (+0000) Subject: AMDGPU: Remove mubuf specific PatFrags X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=92b9f2ca122ee4e51fc31cb947450bccefbf76ae;p=llvm AMDGPU: Remove mubuf specific PatFrags These are identical to the *_global PatFrag, and will only create more work to get the GlobalISel importer to handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365350 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/BUFInstructions.td b/lib/Target/AMDGPU/BUFInstructions.td index 69bef02b203..02b054f089f 100644 --- a/lib/Target/AMDGPU/BUFInstructions.td +++ b/lib/Target/AMDGPU/BUFInstructions.td @@ -17,20 +17,6 @@ def MUBUFOffset : ComplexPattern; def MUBUFOffsetNoGLC : ComplexPattern; def MUBUFOffsetAtomic : ComplexPattern; -class MubufLoad : PatFrag < - (ops node:$ptr), (op node:$ptr), [{ - auto const AS = cast(N)->getAddressSpace(); - return AS == AMDGPUAS::GLOBAL_ADDRESS || - AS == AMDGPUAS::CONSTANT_ADDRESS; -}]>; - -def mubuf_load : MubufLoad ; -def mubuf_az_extloadi8 : MubufLoad ; -def mubuf_sextloadi8 : MubufLoad ; -def mubuf_az_extloadi16 : MubufLoad ; -def mubuf_sextloadi16 : MubufLoad ; -def mubuf_load_atomic : MubufLoad ; - def BUFAddrKind { int Offset = 0; int OffEn = 1; @@ -833,28 +819,28 @@ let SubtargetPredicate = HasPackedD16VMem, D16Buf = 1 in { } // End HasPackedD16VMem. defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads_Lds < - "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8 + "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global >; defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads_Lds < - "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8 + "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global >; defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads_Lds < - "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16 + "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global >; defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads_Lds < - "buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16 + "buffer_load_sshort", VGPR_32, i32, sextloadi16_global >; defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads_Lds < - "buffer_load_dword", VGPR_32, i32, mubuf_load + "buffer_load_dword", VGPR_32, i32, load_global >; defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads < - "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load + "buffer_load_dwordx2", VReg_64, v2i32, load_global >; defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads < - "buffer_load_dwordx3", VReg_96, v3i32, mubuf_load + "buffer_load_dwordx3", VReg_96, v3i32, load_global >; defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads < - "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load + "buffer_load_dwordx4", VReg_128, v4i32, load_global >; // This is not described in AMD documentation, @@ -1387,8 +1373,8 @@ def : MUBUFLoad_PatternADDR64 ; def : MUBUFLoad_PatternADDR64 ; -defm : MUBUFLoad_Atomic_Pattern ; -defm : MUBUFLoad_Atomic_Pattern ; +defm : MUBUFLoad_Atomic_Pattern ; +defm : MUBUFLoad_Atomic_Pattern ; } // End SubtargetPredicate = isGFX6GFX7 multiclass MUBUFLoad_Pattern ; defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; } // End OtherPredicates = [Has16BitInsts]