From: Roman Lebedev Date: Wed, 22 May 2019 13:04:24 +0000 (+0000) Subject: [NFC][SystemZ] Autogenerate alloca-03.ll test to make test changes more visible X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=928e0daca7764c3c85fa83f455c359365c387d42;p=llvm [NFC][SystemZ] Autogenerate alloca-03.ll test to make test changes more visible The check lines are being affected by an upcoming patch, regenerate the checklines to visualize the changes better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361380 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/SystemZ/alloca-03.ll b/test/CodeGen/SystemZ/alloca-03.ll index 05c842f3dc4..343071211b7 100644 --- a/test/CodeGen/SystemZ/alloca-03.ll +++ b/test/CodeGen/SystemZ/alloca-03.ll @@ -1,12 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; Allocate 8 bytes, no need to align stack. define void @f0() { ; CHECK-LABEL: f0: -; CHECK: aghi %r15, -168 -; CHECK-NOT: nil -; CHECK: mvghi 160(%r15), 10 -; CHECK: aghi %r15, 168 +; CHECK: # %bb.0: +; CHECK-NEXT: aghi %r15, -168 +; CHECK-NEXT: .cfi_def_cfa_offset 328 +; CHECK-NEXT: mvghi 160(%r15), 10 +; CHECK-NEXT: aghi %r15, 168 +; CHECK-NEXT: br %r14 %x = alloca i64 store volatile i64 10, i64* %x ret void @@ -15,13 +18,22 @@ define void @f0() { ; Allocate %len * 8, no need to align stack. define void @f1(i64 %len) { ; CHECK-LABEL: f1: -; CHECK-DAG: sllg %r0, %r2, 3 -; CHECK-DAG: lgr %r1, %r15 -; CHECK: sgr %r1, %r0 -; CHECK-NOT: ngr -; CHECK-DAG: lgr %r15, %r1 -; CHECK-DAG: la %r2, 160(%r1) -; CHECK: mvghi 0(%r2), 10 +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r11, %r15, 88(%r15) +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -160 +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: lgr %r11, %r15 +; CHECK-NEXT: .cfi_def_cfa_register %r11 +; CHECK-NEXT: lgr %r1, %r15 +; CHECK-NEXT: sllg %r0, %r2, 3 +; CHECK-NEXT: sgr %r1, %r0 +; CHECK-NEXT: la %r2, 160(%r1) +; CHECK-NEXT: lgr %r15, %r1 +; CHECK-NEXT: mvghi 0(%r2), 10 +; CHECK-NEXT: lmg %r11, %r15, 248(%r11) +; CHECK-NEXT: br %r14 %x = alloca i64, i64 %len store volatile i64 10, i64* %x ret void @@ -30,11 +42,22 @@ define void @f1(i64 %len) { ; Static alloca, align 128. define void @f2() { ; CHECK-LABEL: f2: -; CHECK: aghi %r1, -128 -; CHECK-DAG: lgr %r15, %r1 -; CHECK-DAG: la %r2, 280(%r1) -; CHECK-DAG: nill %r2, 65408 -; CHECK: mvghi 0(%r2), 10 +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r11, %r15, 88(%r15) +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -160 +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: lgr %r11, %r15 +; CHECK-NEXT: .cfi_def_cfa_register %r11 +; CHECK-NEXT: lgr %r1, %r15 +; CHECK-NEXT: aghi %r1, -128 +; CHECK-NEXT: la %r2, 280(%r1) +; CHECK-NEXT: nill %r2, 65408 +; CHECK-NEXT: lgr %r15, %r1 +; CHECK-NEXT: mvghi 0(%r2), 10 +; CHECK-NEXT: lmg %r11, %r15, 248(%r11) +; CHECK-NEXT: br %r14 %x = alloca i64, i64 1, align 128 store volatile i64 10, i64* %x, align 128 ret void @@ -43,14 +66,24 @@ define void @f2() { ; Dynamic alloca, align 128. define void @f3(i64 %len) { ; CHECK-LABEL: f3: -; CHECK-DAG: sllg %r2, %r2, 3 -; CHECK-DAG: la %r0, 120(%r2) -; CHECK-DAG: lgr %r1, %r15 -; CHECK: sgr %r1, %r0 -; CHECK: la %r2, 280(%r1) -; CHECK: nill %r2, 65408 -; CHECK: lgr %r15, %r1 -; CHECK: mvghi 0(%r2), 10 +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r11, %r15, 88(%r15) +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -160 +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: lgr %r11, %r15 +; CHECK-NEXT: .cfi_def_cfa_register %r11 +; CHECK-NEXT: lgr %r1, %r15 +; CHECK-NEXT: sllg %r2, %r2, 3 +; CHECK-NEXT: la %r0, 120(%r2) +; CHECK-NEXT: sgr %r1, %r0 +; CHECK-NEXT: la %r2, 280(%r1) +; CHECK-NEXT: nill %r2, 65408 +; CHECK-NEXT: lgr %r15, %r1 +; CHECK-NEXT: mvghi 0(%r2), 10 +; CHECK-NEXT: lmg %r11, %r15, 248(%r11) +; CHECK-NEXT: br %r14 %x = alloca i64, i64 %len, align 128 store volatile i64 10, i64* %x, align 128 ret void @@ -59,9 +92,12 @@ define void @f3(i64 %len) { ; Static alloca w/out alignment - part of frame. define void @f4() { ; CHECK-LABEL: f4: -; CHECK: aghi %r15, -168 -; CHECK: mvhi 164(%r15), 10 -; CHECK: aghi %r15, 168 +; CHECK: # %bb.0: +; CHECK-NEXT: aghi %r15, -168 +; CHECK-NEXT: .cfi_def_cfa_offset 328 +; CHECK-NEXT: mvhi 164(%r15), 10 +; CHECK-NEXT: aghi %r15, 168 +; CHECK-NEXT: br %r14 %x = alloca i32 store volatile i32 10, i32* %x ret void @@ -70,15 +106,23 @@ define void @f4() { ; Static alloca of one i32, aligned by 128. define void @f5() { ; CHECK-LABEL: f5: - -; CHECK: lgr %r1, %r15 -; CHECK: aghi %r1, -128 -; CHECK: la %r2, 280(%r1) -; CHECK: nill %r2, 65408 -; CHECK: lgr %r15, %r1 -; CHECK: mvhi 0(%r2), 10 +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r11, %r15, 88(%r15) +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -160 +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: lgr %r11, %r15 +; CHECK-NEXT: .cfi_def_cfa_register %r11 +; CHECK-NEXT: lgr %r1, %r15 +; CHECK-NEXT: aghi %r1, -128 +; CHECK-NEXT: la %r2, 280(%r1) +; CHECK-NEXT: nill %r2, 65408 +; CHECK-NEXT: lgr %r15, %r1 +; CHECK-NEXT: mvhi 0(%r2), 10 +; CHECK-NEXT: lmg %r11, %r15, 248(%r11) +; CHECK-NEXT: br %r14 %x = alloca i32, i64 1, align 128 store volatile i32 10, i32* %x ret void } -