From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 23 Apr 2019 11:11:34 +0000 (+0000)
Subject: Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=9190263693221f8d2f58cbd39355c3cd8937199a;p=llvm

Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358969 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 23d8adcde39..3b27b9f5b02 100644
--- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -710,7 +710,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSigned
       if (IsSignedImm) {
         int64_t RHSC = RHS->getSExtValue();
         unsigned Scale = Log2_32(Size);
-        int64_t Range = 0x1 << (BW-1);
+        int64_t Range = 0x1LL << (BW - 1);
 
         if ((RHSC & (Size - 1)) == 0 && RHSC >= -(Range << Scale) &&
             RHSC < (Range << Scale)) {
@@ -726,7 +726,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSigned
         // unsigned Immediate
         uint64_t RHSC = RHS->getZExtValue();
         unsigned Scale = Log2_32(Size);
-        uint64_t Range = 0x1 << BW;
+        uint64_t Range = 0x1ULL << BW;
 
         if ((RHSC & (Size - 1)) == 0 && RHSC < (Range << Scale)) {
           Base = N.getOperand(0);