From: Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Date: Fri, 15 Feb 2019 18:28:11 +0000 (+0000)
Subject: [MCA] Improved code comment. NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=91735b456996e82a7f5d3224692e3e58cec48578;p=llvm

[MCA] Improved code comment. NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354154 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/MCA/HardwareUnits/Scheduler.h b/include/llvm/MCA/HardwareUnits/Scheduler.h
index f1cfcbe6b2b..dc630eea5b6 100644
--- a/include/llvm/MCA/HardwareUnits/Scheduler.h
+++ b/include/llvm/MCA/HardwareUnits/Scheduler.h
@@ -80,24 +80,26 @@ class Scheduler : public HardwareUnit {
   // the instruction stage (see Instruction::InstrStage).
   //
   // An Instruction dispatched to the Scheduler is added to the WaitSet if not
-  // all its register operands are available, and at least one latency is unknown.
-  // By construction, the WaitSet only contains instructions that are in the
-  // IS_DISPATCHED stage.
+  // all its register operands are available, and at least one latency is
+  // unknown.  By construction, the WaitSet only contains instructions that are
+  // in the IS_DISPATCHED stage.
   //
   // An Instruction transitions from the WaitSet to the PendingSet if the
-  // instruction is not ready yet, but the latency of every register read is known.
-  // Instructions in the PendingSet are expected to be in the IS_PENDING stage.
+  // instruction is not ready yet, but the latency of every register read is
+  // known.  Instructions in the PendingSet can only be in the IS_PENDING or
+  // IS_READY stage.  Only IS_READY instructions that are waiting on memory
+  // dependencies can be added to the PendingSet.
   //
   // Instructions in the PendingSet are immediately dominated only by
-  // instructions that have already been issued to the underlying pipelines.
-  // In the presence of bottlenecks caused by data dependencies, the PendingSet
-  // can be inspected to identify problematic data dependencies between
+  // instructions that have already been issued to the underlying pipelines.  In
+  // the presence of bottlenecks caused by data dependencies, the PendingSet can
+  // be inspected to identify problematic data dependencies between
   // instructions.
   //
   // An instruction is moved to the ReadySet when all register operands become
   // available, and all memory dependencies are met.  Instructions that are
-  // moved from the PendingSet to the ReadySet transition in state from
-  // 'IS_PENDING' to 'IS_READY'.
+  // moved from the PendingSet to the ReadySet must transition to the 'IS_READY'
+  // stage.
   //
   // On every cycle, the Scheduler checks if it can promote instructions from the
   // PendingSet to the ReadySet.
diff --git a/lib/MCA/Instruction.cpp b/lib/MCA/Instruction.cpp
index 1722ce08f69..b1508a0ade0 100644
--- a/lib/MCA/Instruction.cpp
+++ b/lib/MCA/Instruction.cpp
@@ -127,7 +127,8 @@ void Instruction::dispatch(unsigned RCUToken) {
   RCUTokenID = RCUToken;
 
   // Check if input operands are already available.
-  update();
+  if (updateDispatched())
+    updatePending();
 }
 
 void Instruction::execute() {