From: Zachary Turner Date: Fri, 5 Apr 2019 18:06:42 +0000 (+0000) Subject: Try to fix Sphinx bot. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=90e8e811996ac0518345be21d653e21c8f1498e3;p=llvm Try to fix Sphinx bot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357790 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst index 33a486ee8fc..38a8cbf2b7d 100644 --- a/docs/AMDGPUUsage.rst +++ b/docs/AMDGPUUsage.rst @@ -433,14 +433,12 @@ The AMDGPU backend supports the following LLVM IR attributes. "amdgpu-waves-per-eu"="m,n" Specify the minimum and maximum number of waves per execution unit. Generated by the ``amdgpu_waves_per_eu`` CLANG attribute [CLANG-ATTR]_. - - "amdgpu-ieee" true/false. Specify whether the function expects - the IEEE field of the mode register to be set on entry. Overrides - the default for the calling convention. - "amdgpu-dx10-clamp" true/false. Specify whether the function expects - the DX10_CLAMP field of the mode register to be set on entry. Overrides - the default for the calling convention. - + "amdgpu-ieee" true/false. Specify whether the function expects the IEEE field of the + mode register to be set on entry. Overrides the default for + the calling convention. + "amdgpu-dx10-clamp" true/false. Specify whether the function expects the DX10_CLAMP field of + the mode register to be set on entry. Overrides the default + for the calling convention. ======================================= ========================================================== Code Object