From: Diogo N. Sampaio <diogo.sampaio@arm.com>
Date: Thu, 11 Apr 2019 14:19:43 +0000 (+0000)
Subject: [AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=90dd83f805485713b01423043532fb635e77d8fb;p=llvm

[AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64

Summary:  Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64

Reviewers: pbarrio, DavidSpickett, LukeGeeson

Reviewed By: LukeGeeson

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60259



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358171 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index 06d25bb3e37..7dad458d80e 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5327,6 +5327,8 @@ def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), v
           (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
           (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
+          (SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp
             (and FPR32:$Rn, (i32 65535)),
             vecshiftR16:$imm)),
diff --git a/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll b/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
index 19365a6f2f7..04da29888e7 100644
--- a/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
+++ b/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
@@ -342,3 +342,13 @@ entry:
   %0 = trunc i32 %facg to i16
   ret i16 %0
 }
+
+define dso_local half @vcvth_n_f16_s64_test(i64 %a) {
+; CHECK-LABEL: vcvth_n_f16_s64_test:
+; CHECK:       fmov    d0, x0
+; CHECK-NEXT:  scvtf   h0, h0, #16
+; CHECK-NEXT:  ret
+entry:
+  %vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
+  ret half %vcvth_n_f16_s64
+}