From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 16 Sep 2019 14:14:37 +0000 (+0000)
Subject: AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEIL
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8f86794aa2807f3b8fbe948f68a8f9518ba12e23;p=llvm

AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEIL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371991 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7406879405b..92d5a5d07c7 100644
--- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1783,6 +1783,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case AMDGPU::G_FMAD:
   case AMDGPU::G_FSQRT:
   case AMDGPU::G_FFLOOR:
+  case AMDGPU::G_FCEIL:
+  case AMDGPU::G_FRINT:
   case AMDGPU::G_SITOFP:
   case AMDGPU::G_UITOFP:
   case AMDGPU::G_FPTRUNC:
diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
new file mode 100644
index 00000000000..953db08a703
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: fceil_s
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: fceil_s
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[FCEIL_:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = G_FCEIL %0
+...
+
+---
+name: fceil_v
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: fceil_v
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[FCEIL_:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_FCEIL %0
+...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
new file mode 100644
index 00000000000..edf201967fe
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: frint_s
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: frint_s
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[FRINT_:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY]]
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = G_FRINT %0
+...
+
+---
+name: frint_v
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: frint_v
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[FRINT_:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY]]
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_FRINT %0
+...