From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 6 Apr 2017 04:02:33 +0000 (+0000)
Subject: [IR] Add commutable matchers for Add and Mul to go with the logic operations that... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8f5aadd46518ab5f8854591c79dd000f1c99c787;p=llvm

[IR] Add commutable matchers for Add and Mul to go with the logic operations that are already present. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299620 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/IR/PatternMatch.h b/include/llvm/IR/PatternMatch.h
index 62e1d61e818..34f3724805b 100644
--- a/include/llvm/IR/PatternMatch.h
+++ b/include/llvm/IR/PatternMatch.h
@@ -1357,6 +1357,22 @@ m_c_ICmp(ICmpInst::Predicate &Pred, const LHS &L, const RHS &R) {
   return m_CombineOr(m_ICmp(Pred, L, R), m_ICmp(Pred, R, L));
 }
 
+/// \brief Matches a Add with LHS and RHS in either order.
+template<typename LHS, typename RHS>
+inline match_combine_or<BinaryOp_match<LHS, RHS, Instruction::Add>,
+                        BinaryOp_match<RHS, LHS, Instruction::Add>>
+m_c_Add(const LHS &L, const RHS &R) {
+  return m_CombineOr(m_Add(L, R), m_Add(R, L));
+}
+
+/// \brief Matches a Mul with LHS and RHS in either order.
+template<typename LHS, typename RHS>
+inline match_combine_or<BinaryOp_match<LHS, RHS, Instruction::Mul>,
+                        BinaryOp_match<RHS, LHS, Instruction::Mul>>
+m_c_Mul(const LHS &L, const RHS &R) {
+  return m_CombineOr(m_Mul(L, R), m_Mul(R, L));
+}
+
 /// \brief Matches an And with LHS and RHS in either order.
 template<typename LHS, typename RHS>
 inline match_combine_or<BinaryOp_match<LHS, RHS, Instruction::And>,