From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 19 Jun 2019 18:34:58 +0000 (+0000)
Subject: [TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8f0c7afb49594d54306e2ed7f2c498e0a7a3100b;p=llvm

[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support

Move 'lowest' demanded elt -> bitcast fold out of ZERO_EXTEND_VECTOR_INREG into ANY_EXTEND_VECTOR_INREG case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363856 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b08a41b3d08..b55d37024de 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1381,19 +1381,11 @@ bool TargetLowering::SimplifyDemandedBits(
     bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
 
     // If none of the top bits are demanded, convert this into an any_extend.
-    if (DemandedBits.getActiveBits() <= InBits) {
-      // If we only need the non-extended bits of the bottom element
-      // then we can just bitcast to the result.
-      if (IsVecInReg && DemandedElts == 1 &&
-          VT.getSizeInBits() == SrcVT.getSizeInBits() &&
-          TLO.DAG.getDataLayout().isLittleEndian())
-        return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
-
+    if (DemandedBits.getActiveBits() <= InBits)
       return TLO.CombineTo(
           Op, TLO.DAG.getNode(IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG
                                          : ISD::ANY_EXTEND,
                               dl, VT, Src));
-    }
 
     APInt InDemandedBits = DemandedBits.trunc(InBits);
     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
@@ -1444,12 +1436,21 @@ bool TargetLowering::SimplifyDemandedBits(
                               dl, VT, Src));
     break;
   }
-  case ISD::ANY_EXTEND: {
-    // TODO: Add ISD::ANY_EXTEND_VECTOR_INREG support.
+  case ISD::ANY_EXTEND:
+  case ISD::ANY_EXTEND_VECTOR_INREG: {
     SDValue Src = Op.getOperand(0);
     EVT SrcVT = Src.getValueType();
     unsigned InBits = SrcVT.getScalarSizeInBits();
     unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
+    bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
+
+    // If we only need the bottom element then we can just bitcast.
+    // TODO: Handle ANY_EXTEND?
+    if (IsVecInReg && DemandedElts == 1 &&
+        VT.getSizeInBits() == SrcVT.getSizeInBits() &&
+        TLO.DAG.getDataLayout().isLittleEndian())
+      return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
+
     APInt InDemandedBits = DemandedBits.trunc(InBits);
     APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
     if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,