From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 2 Feb 2017 04:17:15 +0000 (+0000)
Subject: [AVX-512] Add test case demonstrating that we have an incomplete implicit def list... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8dabf9ee24a00298c1ebddbf661e0c19013513cf;p=llvm

[AVX-512] Add test case demonstrating that we have an incomplete implicit def list for VZEROALL/VZEROUPPER. YMM16-YMM31 should also be defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293861 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/avx-intrinsics-x86_64.ll b/test/CodeGen/X86/avx-intrinsics-x86_64.ll
index 6874181dded..9f18c0930fd 100644
--- a/test/CodeGen/X86/avx-intrinsics-x86_64.ll
+++ b/test/CodeGen/X86/avx-intrinsics-x86_64.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx512vl | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
 
 define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
 ; CHECK-LABEL: test_x86_sse2_cvtsd2si64:
@@ -67,4 +67,44 @@ define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
 }
 declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
 
+define <4 x double> @test_x86_avx_vzeroall(<4 x double> %a, <4 x double> %b) {
+; AVX-LABEL: test_x86_avx_vzeroall:
+; AVX:       ## BB#0:
+; AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmovupd %ymm0, -{{[0-9]+}}(%rsp) ## 32-byte Spill
+; AVX-NEXT:    vzeroall
+; AVX-NEXT:    vmovups -{{[0-9]+}}(%rsp), %ymm0 ## 32-byte Reload
+; AVX-NEXT:    retq
+;
+; AVX512VL-LABEL: test_x86_avx_vzeroall:
+; AVX512VL:       ## BB#0:
+; AVX512VL-NEXT:    vaddpd %ymm1, %ymm0, %ymm16
+; AVX512VL-NEXT:    vzeroall
+; AVX512VL-NEXT:    vmovapd %ymm16, %ymm0
+; AVX512VL-NEXT:    retq
+  %c = fadd <4 x double> %a, %b
+  call void @llvm.x86.avx.vzeroall()
+  ret <4 x double> %c
+}
+declare void @llvm.x86.avx.vzeroall() nounwind
 
+define <4 x double> @test_x86_avx_vzeroupper(<4 x double> %a, <4 x double> %b) {
+; AVX-LABEL: test_x86_avx_vzeroupper:
+; AVX:       ## BB#0:
+; AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmovupd %ymm0, -{{[0-9]+}}(%rsp) ## 32-byte Spill
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    vmovups -{{[0-9]+}}(%rsp), %ymm0 ## 32-byte Reload
+; AVX-NEXT:    retq
+;
+; AVX512VL-LABEL: test_x86_avx_vzeroupper:
+; AVX512VL:       ## BB#0:
+; AVX512VL-NEXT:    vaddpd %ymm1, %ymm0, %ymm16
+; AVX512VL-NEXT:    vzeroupper
+; AVX512VL-NEXT:    vmovapd %ymm16, %ymm0
+; AVX512VL-NEXT:    retq
+  %c = fadd <4 x double> %a, %b
+  call void @llvm.x86.avx.vzeroupper()
+  ret <4 x double> %c
+}
+declare void @llvm.x86.avx.vzeroupper() nounwind