From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Thu, 5 May 2016 18:38:35 +0000 (+0000)
Subject: [Hexagon] Add aliases for vector loads/stores with no explicit offset
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8cb434aecfa3f5a2515d837b2a9745da20c60c67;p=llvm

[Hexagon] Add aliases for vector loads/stores with no explicit offset

The mem(r0) instructions are treated as mem(r0+#0).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268661 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonInstrAlias.td b/lib/Target/Hexagon/HexagonInstrAlias.td
index ab3d8db7439..e384e374f4d 100644
--- a/lib/Target/Hexagon/HexagonInstrAlias.td
+++ b/lib/Target/Hexagon/HexagonInstrAlias.td
@@ -541,3 +541,82 @@ def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
 def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
       (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
       Requires<[HasV60T]>;
+
+// Mapping from vtrans2x2(Vy32,Vx32,Rt32) to vshuff(Vy32,Vx32,Rt32)
+def : InstAlias<"vtrans2x2($Vy, $Vx, $Rt)",
+      (V6_vshuff VectorRegs:$Vy, VectorRegs:$Vx, IntRegs:$Rt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"$Vt=vmem($Rs)",
+      (V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"$Vt=vmem($Rs):nt",
+      (V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"vmem($Rs)=$Vt",
+      (V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"vmem($Rs):nt=$Vt",
+      (V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"vmem($Rs)=$Vt.new",
+      (V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"vmem($Rs):nt=$Vt.new",
+      (V6_vS32b_nt_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if ($Qv) vmem($Rs)=$Vt",
+      (V6_vS32b_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if (!$Qv) vmem($Rs)=$Vt",
+      (V6_vS32b_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if ($Qv) vmem($Rs):nt=$Vt",
+      (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if (!$Qv) vmem($Rs):nt=$Vt",
+      (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if ($Pv) vmem($Rs)=$Vt",
+      (V6_vS32b_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if (!$Pv) vmem($Rs)=$Vt",
+      (V6_vS32b_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if ($Pv) vmem($Rs):nt=$Vt",
+      (V6_vS32b_nt_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if (!$Pv) vmem($Rs):nt=$Vt",
+      (V6_vS32b_nt_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"$Vt=vmemu($Rs)",
+      (V6_vL32Ub_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"vmemu($Rs)=$Vt",
+      (V6_vS32Ub_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if ($Pv) vmemu($Rs)=$Vt",
+      (V6_vS32Ub_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+def : InstAlias<"if (!$Pv) vmemu($Rs)=$Vt",
+      (V6_vS32Ub_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
+      Requires<[HasV60T]>;
+
+
diff --git a/test/MC/Hexagon/v60-misc.s b/test/MC/Hexagon/v60-misc.s
index b562010a486..5094715ceba 100644
--- a/test/MC/Hexagon/v60-misc.s
+++ b/test/MC/Hexagon/v60-misc.s
@@ -44,3 +44,64 @@ q2 |= vcmp.eq(v11.uw, v12.uw)
 
 # CHECK: 1c8eed8b { q3 ^= vcmp.eq(v13.w,v14.w) }
 q3 ^= vcmp.eq(v13.uw, v14.uw)
+
+# CHECK: 2800c00f { v15 = vmem(r0+#0) }
+v15 = vmem(r0)
+
+# CHECK: 2841c010 { v16 = vmem(r1+#0):nt }
+v16 = vmem(r1):nt
+
+# CHECK: 2822c011 { vmem(r2+#0) = v17 }
+vmem(r2) = v17
+
+# CHECK: 2863c012 { vmem(r3+#0):nt = v18 }
+vmem(r3):nt = v18
+
+# CHECK: 2884c013 { if (q0) vmem(r4+#0) = v19 }
+if (q0) vmem(r4) = v19
+
+# CHECK: 2885c834 { if (!q1) vmem(r5+#0) = v20 }
+if (!q1) vmem(r5) = v20
+
+# CHECK: 28c6d015 { if (q2) vmem(r6+#0):nt = v21 }
+if (q2) vmem(r6):nt = v21
+
+# CHECK: 28c7d836 { if (!q3) vmem(r7+#0):nt = v22 }
+if (!q3) vmem(r7):nt = v22
+
+# CHECK: 28a8c017 { if (p0) vmem(r8+#0) = v23 }
+if (p0) vmem(r8) = v23
+
+# CHECK: 28a9c838 { if (!p1) vmem(r9+#0) = v24 }
+if (!p1) vmem(r9) = v24
+
+# CHECK: 28ead019 { if (p2) vmem(r10+#0):nt = v25 }
+if (p2) vmem(r10):nt = v25
+
+# CHECK: 28ebd83a { if (!p3) vmem(r11+#0):nt = v26 }
+if (!p3) vmem(r11):nt = v26
+
+# CHECK: 282cc022 vmem(r12+#0) = v27.new
+{
+  v27 = vxor(v28, v29)
+  vmem(r12) = v27.new
+}
+
+# CHECK: 286dc022 vmem(r13+#0):nt = v30.new
+{
+  v30 = vxor(v31, v0)
+  vmem(r13):nt = v30.new
+}
+
+# CHECK: 280ec0e1 { v1 = vmemu(r14+#0) }
+v1 = vmemu(r14)
+
+# CHECK: 282fc0e2 { vmemu(r15+#0) = v2 }
+vmemu(r15) = v2
+
+# CHECK: 28b0c0c3 { if (p0) vmemu(r16+#0) = v3 }
+if (p0) vmemu(r16) = v3
+
+# CHECK: 28b1c8e4 { if (!p1) vmemu(r17+#0) = v4 }
+if (!p1) vmemu(r17) = v4
+