From: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Mon, 11 Sep 2017 11:11:17 +0000 (+0000)
Subject: [ARM] Enable the use of SVC anywhere in an IT block
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8bb02cf4a4e7bde5513a70f070cf8fca799a7640;p=llvm

[ARM] Enable the use of SVC anywhere in an IT block

Differential Revision: https://reviews.llvm.org/D37374


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312908 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 5e5931dcf21..43135ad2103 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8717,9 +8717,10 @@ template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
 
-  // All branch & call instructions terminate IT blocks.
-  if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() ||
-      MCID.isBranch() || MCID.isIndirectBranch())
+  // All branch & call instructions terminate IT blocks with the exception of
+  // SVC.
+  if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
+      MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
     return true;
 
   // Any arithmetic instruction which writes to the PC also terminates the IT
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index b1cb53cdace..6f81f00350d 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -3113,12 +3113,18 @@ _func:
         svceq #255
         it ne
         swine #33
+        itt eq
+        svceq #0
+        svceq #1
 
 @ CHECK: svc	#0                      @ encoding: [0x00,0xdf]
 @ CHECK: it	eq                      @ encoding: [0x08,0xbf]
 @ CHECK: svceq	#255                    @ encoding: [0xff,0xdf]
 @ CHECK: it	ne                      @ encoding: [0x18,0xbf]
 @ CHECK: svcne	#33                     @ encoding: [0x21,0xdf]
+@ CHECK: itt    eq                      @ encoding: [0x04,0xbf]
+@ CHECK: svceq  #0                      @ encoding: [0x00,0xdf]
+@ CHECK: svceq  #1                      @ encoding: [0x01,0xdf]
 
 
 @------------------------------------------------------------------------------