From: Craig Topper <craig.topper@intel.com>
Date: Mon, 27 Nov 2017 18:15:14 +0000 (+0000)
Subject: [X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8b3bfa3cd5f67636eb1d072120bd437dd6b7f910;p=llvm

[X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.

I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319066 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 7dd3e638055..36e83881270 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -28343,7 +28343,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
   // Which shuffle domains are permitted?
   // Permit domain crossing at higher combine depths.
   bool AllowFloatDomain = FloatDomain || (Depth > 3);
-  bool AllowIntDomain = (!FloatDomain || (Depth > 3)) &&
+  bool AllowIntDomain = (!FloatDomain || (Depth > 3)) && Subtarget.hasSSE2() &&
                         (!MaskVT.is256BitVector() || Subtarget.hasAVX2());
 
   // Determine zeroable mask elements.