From: Craig Topper <craig.topper@intel.com>
Date: Sun, 10 Dec 2017 17:42:38 +0000 (+0000)
Subject: [X86] Add VPSRLWZrr to skylake server scheduler model.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8a79d6acbd2ed225c6756703be937796d9a843d9;p=llvm

[X86] Add VPSRLWZrr to skylake server scheduler model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320315 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86SchedSkylakeServer.td b/lib/Target/X86/X86SchedSkylakeServer.td
index 8b46cb8eabc..388df27f2af 100755
--- a/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/lib/Target/X86/X86SchedSkylakeServer.td
@@ -3000,6 +3000,7 @@ def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLQZ256rr(b?)(k?)(z?)")>;
 def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLQZrr(b?)(k?)(z?)")>;
 def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLWYrr")>;
 def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLWZ256rr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLWZrr(b?)(k?)(z?)")>;
 
 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
   let Latency = 4;