From: Simon Atanasyan <simon@atanasyan.com>
Date: Wed, 3 Jul 2019 10:33:09 +0000 (+0000)
Subject: [mips] Add missing mips16 instructions to general scheduling definitions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8a0fb666cca3abb9c5aef36f4e2fd70f0df171a6;p=llvm

[mips] Add missing mips16 instructions to general scheduling definitions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365022 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td
index fff9f6ad02f..36b6c73d100 100644
--- a/lib/Target/Mips/Mips16InstrInfo.td
+++ b/lib/Target/Mips/Mips16InstrInfo.td
@@ -483,13 +483,11 @@ class SelT<string op1, string op2>:
 //
 // 32 bit constant
 //
-def Constant32:
-  MipsPseudo16<(outs), (ins simm32:$imm), "\t.word $imm", []>;
+def Constant32 : MipsPseudo16<(outs), (ins simm32:$imm), "\t.word $imm", []>;
 
-def LwConstant32:
+def LwConstant32 :
   MipsPseudo16<(outs CPU16Regs:$rx), (ins simm32:$imm, simm32:$constid),
-    "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
-
+               "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
 
 //
 // Some general instruction class info
diff --git a/lib/Target/Mips/MipsScheduleGeneric.td b/lib/Target/Mips/MipsScheduleGeneric.td
index 780feb34b04..4f3afeb720d 100644
--- a/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/lib/Target/Mips/MipsScheduleGeneric.td
@@ -79,6 +79,9 @@ def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
                                  SraX16, SrlvRxRy16, SrlX16, SubuRxRyRz16,
                                  XorRxRxRy16)>;
 
+def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
+                                 GotPrologue16, CONSTPOOL_ENTRY)>;
+
 // microMIPS
 // =========