From: Roman Lebedev <lebedev.ri@gmail.com>
Date: Wed, 22 May 2019 15:34:51 +0000 (+0000)
Subject: [NFC][ARM] Autogenerate addsubcarry-promotion.ll test
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8911830f0835c0e2fcd9ab56d5543d893f16b583;p=llvm

[NFC][ARM] Autogenerate addsubcarry-promotion.ll test

Being affected by upcoming patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361397 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/ARM/addsubcarry-promotion.ll b/test/CodeGen/ARM/addsubcarry-promotion.ll
index 8b99b2ada7c..454b4b37f01 100644
--- a/test/CodeGen/ARM/addsubcarry-promotion.ll
+++ b/test/CodeGen/ARM/addsubcarry-promotion.ll
@@ -1,45 +1,55 @@
-; RUN: llc -O2 -mtriple armv7a < %s | FileCheck --check-prefix=ARM %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O2 -mtriple armv7a < %s | FileCheck --check-prefixes=ARM,ARMV7A %s
 
-; RUN: llc -O2 -mtriple thumbv6m < %s | FileCheck --check-prefix=THUMB1 %s
-; RUN: llc -O2 -mtriple thumbv8m.base < %s | FileCheck --check-prefix=THUMB1 %s
+; RUN: llc -O2 -mtriple thumbv6m < %s | FileCheck --check-prefixes=THUMB1,THUMBV6M %s
+; RUN: llc -O2 -mtriple thumbv8m.base < %s | FileCheck --check-prefixes=THUMB1,THUMBV8M.BASE %s
 
-; RUN: llc -O2 -mtriple thumbv7a < %s | FileCheck --check-prefix=THUMB %s
-; RUN: llc -O2 -mtriple thumbv8m.main < %s | FileCheck --check-prefix=THUMB %s
+; RUN: llc -O2 -mtriple thumbv7a < %s | FileCheck --check-prefixes=THUMB,THUMBV7A %s
+; RUN: llc -O2 -mtriple thumbv8m.main < %s | FileCheck --check-prefixes=THUMB,THUMBV8M.MAIN %s
 
 define void @fn1(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {
+; ARM-LABEL: fn1:
+; ARM:       @ %bb.0: @ %entry
+; ARM-NEXT:    rsb r2, r2, #1
+; ARM-NEXT:    adds r0, r1, r0
+; ARM-NEXT:    movw r1, #65535
+; ARM-NEXT:    sxth r2, r2
+; ARM-NEXT:    adc r0, r2, #0
+; ARM-NEXT:    tst r0, r1
+; ARM-NEXT:    bxeq lr
+; ARM-NEXT:  .LBB0_1: @ %for.cond
+; ARM-NEXT:    @ =>This Inner Loop Header: Depth=1
+; ARM-NEXT:    b .LBB0_1
+;
+; THUMB1-LABEL: fn1:
+; THUMB1:       @ %bb.0: @ %entry
+; THUMB1-NEXT:    movs r3, #1
+; THUMB1-NEXT:    subs r2, r3, r2
+; THUMB1-NEXT:    sxth r2, r2
+; THUMB1-NEXT:    movs r3, #0
+; THUMB1-NEXT:    adds r0, r1, r0
+; THUMB1-NEXT:    adcs r3, r2
+; THUMB1-NEXT:    lsls r0, r3, #16
+; THUMB1-NEXT:    beq .LBB0_2
+; THUMB1-NEXT:  .LBB0_1: @ %for.cond
+; THUMB1-NEXT:    @ =>This Inner Loop Header: Depth=1
+; THUMB1-NEXT:    b .LBB0_1
+; THUMB1-NEXT:  .LBB0_2: @ %if.end
+; THUMB1-NEXT:    bx lr
+;
+; THUMB-LABEL: fn1:
+; THUMB:       @ %bb.0: @ %entry
+; THUMB-NEXT:    rsb.w r2, r2, #1
+; THUMB-NEXT:    adds r0, r0, r1
+; THUMB-NEXT:    sxth r2, r2
+; THUMB-NEXT:    adc r0, r2, #0
+; THUMB-NEXT:    lsls r0, r0, #16
+; THUMB-NEXT:    it eq
+; THUMB-NEXT:    bxeq lr
+; THUMB-NEXT:  .LBB0_1: @ %for.cond
+; THUMB-NEXT:    @ =>This Inner Loop Header: Depth=1
+; THUMB-NEXT:    b .LBB0_1
 entry:
-
-; ARM: rsb	r2, r2, #1
-; ARM: adds	r0, r1, r0
-; ARM: movw	r1, #65535
-; ARM: sxth	r2, r2
-; ARM: adc	r0, r2, #0
-; ARM: tst	r0, r1
-; ARM: bxeq	lr
-; ARM: .LBB0_1:
-; ARM: b	.LBB0_1
-
-; THUMB1: movs	r3, #1
-; THUMB1: subs	r2, r3, r2
-; THUMB1: sxth	r2, r2
-; THUMB1: movs	r3, #0
-; THUMB1: adds	r0, r1, r0
-; THUMB1: adcs	r3, r2
-; THUMB1: lsls	r0, r3, #16
-; THUMB1: beq	.LBB0_2
-; THUMB1: .LBB0_1:
-; THUMB1: b	.LBB0_1
-
-; THUMB: rsb.w	r2, r2, #1
-; THUMB: adds	r0, r0, r1
-; THUMB: sxth	r2, r2
-; THUMB: adc	r0, r2, #0
-; THUMB: lsls	r0, r0, #16
-; THUMB: it	eq
-; THUMB: bxeq	lr
-; THUMB: .LBB0_1:
-; THUMB: b	.LBB0_1
-
   %add = add i32 %b, %a
   %cmp = icmp ult i32 %add, %b
   %conv = zext i1 %cmp to i32