From: Alina Sbirlea <asbirlea@google.com>
Date: Thu, 15 Aug 2019 21:20:08 +0000 (+0000)
Subject: [MemorySSA] Remove restrictive asserts.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=88ca570919206a6497a9e5251f233e73fb399ea6;p=llvm

[MemorySSA] Remove restrictive asserts.

The verification I added has overly restrictive asserts.
Unreachable blocks can have any incoming value in practice, after an
update due to a "replaceAllUses" call when the repalced entry is
LiveOnEntry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369050 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Analysis/MemorySSA.cpp b/lib/Analysis/MemorySSA.cpp
index 26e3cd70161..62bd19133b7 100644
--- a/lib/Analysis/MemorySSA.cpp
+++ b/lib/Analysis/MemorySSA.cpp
@@ -1886,8 +1886,6 @@ void MemorySSA::verifyPrevDefInPhis(Function &F) const {
             }
             DTNode = DTNode->getIDom();
           }
-          assert((DTNode || IncAcc == getLiveOnEntryDef()) &&
-                 "Expected LoE inc");
         } else if (auto *DefList = getBlockDefs(Pred)) {
           // If Pred has unreachable predecessors, but has at least a Def, the
           // incoming access can be the last Def in Pred, or it could have been
@@ -1897,8 +1895,7 @@ void MemorySSA::verifyPrevDefInPhis(Function &F) const {
                  "Incorrect incoming access into phi.");
         } else {
           // If Pred has unreachable predecessors and no Defs, incoming access
-          // should be LoE.
-          assert(IncAcc == getLiveOnEntryDef() && "Expected LoE inc");
+          // should be LoE; In practice, after an update, it may be any access.
         }
       }
     }