From: Zvi Rackover Date: Wed, 26 Jul 2017 08:06:58 +0000 (+0000) Subject: TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef.... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8849d30d5f8d21d872fb78e35ae5b2b302113ab0;p=llvm TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef. NFCI. Changing mask argument type from const SmallVectorImpl& to ArrayRef. This came up in D35700 where a mask is received as an ArrayRef and we want to pass it to TargetLowering::isShuffleMaskLegal(). Also saves a few lines of code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309085 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 525037903b2..a522e50be67 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -733,8 +733,7 @@ public: /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be /// legal. - virtual bool isShuffleMaskLegal(const SmallVectorImpl &/*Mask*/, - EVT /*VT*/) const { + virtual bool isShuffleMaskLegal(ArrayRef /*Mask*/, EVT /*VT*/) const { return true; } diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 04bc38ce2aa..440f35038d3 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -6912,8 +6912,7 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, return SDValue(); } -bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl &M, - EVT VT) const { +bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef M, EVT VT) const { if (VT.getVectorNumElements() == 4 && (VT.is128BitVector() || VT.is64BitVector())) { unsigned PFIndexes[4]; diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h index 0eb80d03938..1b36a56aa16 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.h +++ b/lib/Target/AArch64/AArch64ISelLowering.h @@ -290,7 +290,7 @@ public: /// Return true if the given shuffle mask can be codegen'd directly, or if it /// should be stack expanded. - bool isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const override; + bool isShuffleMaskLegal(ArrayRef M, EVT VT) const override; /// Return the ISD::SETCC ValueType. EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 6ca8cd104bd..56db67c20f4 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -528,8 +528,7 @@ const SISubtarget *SITargetLowering::getSubtarget() const { // TargetLowering queries //===----------------------------------------------------------------------===// -bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl &, - EVT) const { +bool SITargetLowering::isShuffleMaskLegal(ArrayRef, EVT) const { // SI has some legal vector types, but no legal vector operations. Say no // shuffles are legal in order to prefer scalarizing some vector operations. return false; diff --git a/lib/Target/AMDGPU/SIISelLowering.h b/lib/Target/AMDGPU/SIISelLowering.h index e0136e97a56..30482dc6a0a 100644 --- a/lib/Target/AMDGPU/SIISelLowering.h +++ b/lib/Target/AMDGPU/SIISelLowering.h @@ -140,8 +140,7 @@ public: const SISubtarget *getSubtarget() const; - bool isShuffleMaskLegal(const SmallVectorImpl &/*Mask*/, - EVT /*VT*/) const override; + bool isShuffleMaskLegal(ArrayRef /*Mask*/, EVT /*VT*/) const override; bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned IntrinsicID) const override; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 6d9a32c9956..a6317957b68 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -6520,9 +6520,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, /// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// are assumed to be legal. -bool -ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl &M, - EVT VT) const { +bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef M, EVT VT) const { if (VT.getVectorNumElements() == 4 && (VT.is128BitVector() || VT.is64BitVector())) { unsigned PFIndexes[4]; diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 8d73b2ed75e..6ccd4b87000 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -440,7 +440,7 @@ class InstrItineraryData; Sched::Preference getSchedulingPreference(SDNode *N) const override; bool - isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const override; + isShuffleMaskLegal(ArrayRef M, EVT VT) const override; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; /// isFPImmLegal - Returns true if the target can instruction select the diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index f02cd6d3992..364973b088b 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2278,8 +2278,8 @@ static StridedLoadKind isStridedLoad(const ArrayRef &Mask) { return StridedLoadKind::NoPattern; } -bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl &Mask, - EVT VT) const { +bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef Mask, + EVT VT) const { if (Subtarget.useHVXOps()) return isStridedLoad(Mask) != StridedLoadKind::NoPattern; return true; diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 1b1462cce5a..b903ef6e424 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -113,8 +113,7 @@ namespace HexagonISD { bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override; - bool isShuffleMaskLegal(const SmallVectorImpl &Mask, EVT VT) - const override; + bool isShuffleMaskLegal(ArrayRef Mask, EVT VT) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; const char *getTargetNodeName(unsigned Opcode) const override; diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h index 15b474e7f34..3ee6f93d513 100644 --- a/lib/Target/Mips/MipsSEISelLowering.h +++ b/lib/Target/Mips/MipsSEISelLowering.h @@ -43,8 +43,7 @@ namespace llvm { EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; - bool isShuffleMaskLegal(const SmallVectorImpl &Mask, - EVT VT) const override { + bool isShuffleMaskLegal(ArrayRef Mask, EVT VT) const override { return false; } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 0a1400fd272..5d04a8567f8 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -24888,9 +24888,7 @@ bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { /// VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// are assumed to be legal. -bool -X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl &M, - EVT VT) const { +bool X86TargetLowering::isShuffleMaskLegal(ArrayRef M, EVT VT) const { if (!VT.isSimple()) return false; diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 0c1284b7901..d96c5348ea9 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -978,8 +978,7 @@ namespace llvm { /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to /// be legal. - bool isShuffleMaskLegal(const SmallVectorImpl &Mask, - EVT VT) const override; + bool isShuffleMaskLegal(ArrayRef Mask, EVT VT) const override; /// Similar to isShuffleMaskLegal. This is used by Targets can use this to /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to