From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 1 Oct 2019 02:07:19 +0000 (+0000)
Subject: AMDGPU/GlobalISel: Allow scc/vcc alternative mappings for s1 constants
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=87ccb2d847181741313c0f86d797d9fba822553e;p=llvm

AMDGPU/GlobalISel: Allow scc/vcc alternative mappings for s1 constants

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373295 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 82268233976..da690c37c56 100644
--- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -343,7 +343,21 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
 
   InstructionMappings AltMappings;
   switch (MI.getOpcode()) {
-  case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_CONSTANT: {
+    unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
+    if (Size == 1) {
+      static const OpRegBankEntry<1> Table[4] = {
+        { { AMDGPU::VGPRRegBankID }, 1 },
+        { { AMDGPU::SGPRRegBankID }, 1 },
+        { { AMDGPU::VCCRegBankID }, 1 },
+        { { AMDGPU::SCCRegBankID }, 1 }
+      };
+
+      return addMappingFromTable<1>(MI, MRI, { 0 }, Table);
+    }
+
+    LLVM_FALLTHROUGH;
+  }
   case TargetOpcode::G_FCONSTANT:
   case TargetOpcode::G_FRAME_INDEX:
   case TargetOpcode::G_GLOBAL_VALUE: {