From: Sam Tebbs Date: Fri, 13 Sep 2019 09:11:46 +0000 (+0000) Subject: [ARM] Add support for MVE vmaxv and vminv X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8776b6cc6dc2e8553e0762372e9a2975965ada59;p=llvm [ARM] Add support for MVE vmaxv and vminv This patch adds vecreduce_smax, vecredude_umax, vecreduce_smin, vecreduce_umin and selection for vmaxv and minv. Differential Revision: https://reviews.llvm.org/D66413 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371827 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 1abb47afd9a..f42faad7360 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -423,6 +423,10 @@ def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; +def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; +def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; +def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; +def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 4534dbc8ace..d341ee820d3 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -269,6 +269,10 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) { // Vector reductions setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); + setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal); + setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal); + setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal); + setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal); if (!HasMVEFP) { setOperationAction(ISD::SINT_TO_FP, VT, Expand); diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td index 594f928848a..c83ca203b54 100644 --- a/lib/Target/ARM/ARMInstrMVE.td +++ b/lib/Target/ARM/ARMInstrMVE.td @@ -669,6 +669,35 @@ multiclass MVE_VMINMAXV_ty pattern=[]> { defm MVE_VMINV : MVE_VMINMAXV_ty<"vminv", 0b1>; defm MVE_VMAXV : MVE_VMINMAXV_ty<"vmaxv", 0b0>; +let Predicates = [HasMVEInt] in { + def : Pat<(i32 (vecreduce_smax (v16i8 MQPR:$src))), + (i32 (MVE_VMAXVs8 (t2MVNi (i32 127)), $src))>; + def : Pat<(i32 (vecreduce_smax (v8i16 MQPR:$src))), + (i32 (MVE_VMAXVs16 (t2MOVi32imm (i32 -32768)), $src))>; + def : Pat<(i32 (vecreduce_smax (v4i32 MQPR:$src))), + (i32 (MVE_VMAXVs32 (t2MOVi (i32 -2147483648)), $src))>; + def : Pat<(i32 (vecreduce_umax (v16i8 MQPR:$src))), + (i32 (MVE_VMAXVu8 (t2MOVi (i32 0)), $src))>; + def : Pat<(i32 (vecreduce_umax (v8i16 MQPR:$src))), + (i32 (MVE_VMAXVu16 (t2MOVi (i32 0)), $src))>; + def : Pat<(i32 (vecreduce_umax (v4i32 MQPR:$src))), + (i32 (MVE_VMAXVu32 (t2MOVi (i32 0)), $src))>; + + def : Pat<(i32 (vecreduce_smin (v16i8 MQPR:$src))), + (i32 (MVE_VMINVs8 (t2MOVi (i32 127)), $src))>; + def : Pat<(i32 (vecreduce_smin (v8i16 MQPR:$src))), + (i32 (MVE_VMINVs16 (t2MOVi16 (i32 32767)), $src))>; + def : Pat<(i32 (vecreduce_smin (v4i32 MQPR:$src))), + (i32 (MVE_VMINVs32 (t2MVNi (i32 -2147483648)), $src))>; + def : Pat<(i32 (vecreduce_umin (v16i8 MQPR:$src))), + (i32 (MVE_VMINVu8 (t2MOVi (i32 255)), $src))>; + def : Pat<(i32 (vecreduce_umin (v8i16 MQPR:$src))), + (i32 (MVE_VMINVu16 (t2MOVi16 (i32 65535)), $src))>; + def : Pat<(i32 (vecreduce_umin (v4i32 MQPR:$src))), + (i32 (MVE_VMINVu32 (t2MOVi (i32 4294967295)), $src))>; + +} + multiclass MVE_VMINMAXAV_ty pattern=[]> { def s8 : MVE_VMINMAXV; def s16 : MVE_VMINMAXV; diff --git a/lib/Target/ARM/ARMTargetTransformInfo.cpp b/lib/Target/ARM/ARMTargetTransformInfo.cpp index 3dbf5b9efc4..e74b2b1a2ba 100644 --- a/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -1059,11 +1059,11 @@ bool ARMTTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty, case Instruction::Or: case Instruction::Xor: case Instruction::Mul: - case Instruction::ICmp: case Instruction::FCmp: return false; + case Instruction::ICmp: case Instruction::Add: - return ScalarBits * Ty->getVectorNumElements() == 128; + return ScalarBits < 64 && ScalarBits * Ty->getVectorNumElements() == 128; default: llvm_unreachable("Unhandled reduction opcode"); } diff --git a/test/CodeGen/Thumb2/mve-vmaxv.ll b/test/CodeGen/Thumb2/mve-vmaxv.ll new file mode 100644 index 00000000000..8a7ae49f49a --- /dev/null +++ b/test/CodeGen/Thumb2/mve-vmaxv.ll @@ -0,0 +1,135 @@ +; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s + +declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>) +declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>) +declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>) +declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>) +declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>) +declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>) +declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>) +declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>) +declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>) +declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>) +declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>) +declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>) + +define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8_i32(<16 x i8> %s1) { +; CHECK-LABEL: vmaxv_s_v16i8_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: mvn r0, #127 +; CHECK-NEXT: vmaxv.s8 r0, q0 +; CHECK-NEXT: bx lr + %r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %s1) + ret i8 %r +} + +define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16_i32(<8 x i16> %s1) { +; CHECK-LABEL: vmaxv_s_v8i16_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movw r0, #32768 +; CHECK-NEXT: movt r0, #65535 +; CHECK-NEXT: vmaxv.s16 r0, q0 +; CHECK-NEXT: bx lr + %r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %s1) + ret i16 %r +} + +define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1) { +; CHECK-LABEL: vmaxv_s_v4i32_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov.w r0, #-2147483648 +; CHECK-NEXT: vmaxv.s32 r0, q0 +; CHECK-NEXT: bx lr + %r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %s1) + ret i32 %r +} + +define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8_i32(<16 x i8> %s1) { +; CHECK-LABEL: vmaxv_u_v16i8_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: vmaxv.u8 r0, q0 +; CHECK-NEXT: bx lr + %r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %s1) + ret i8 %r +} + +define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16_i32(<8 x i16> %s1) { +; CHECK-LABEL: vmaxv_u_v8i16_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: vmaxv.u16 r0, q0 +; CHECK-NEXT: bx lr + %r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %s1) + ret i16 %r +} + +define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1) { +; CHECK-LABEL: vmaxv_u_v4i32_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: vmaxv.u32 r0, q0 +; CHECK-NEXT: bx lr + %r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %s1) + ret i32 %r +} + +define arm_aapcs_vfpcc i8 @vminv_s_v16i8_i32(<16 x i8> %s1) { +; CHECK-LABEL: vminv_s_v16i8_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #127 +; CHECK-NEXT: vminv.s8 r0, q0 +; CHECK-NEXT: bx lr + %r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %s1) + ret i8 %r +} + +define arm_aapcs_vfpcc i16 @vminv_s_v8i16_i32(<8 x i16> %s1) { +; CHECK-LABEL: vminv_s_v8i16_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movw r0, #32767 +; CHECK-NEXT: vminv.s16 r0, q0 +; CHECK-NEXT: bx lr + %r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %s1) + ret i16 %r +} + +define arm_aapcs_vfpcc i32 @vminv_s_v4i32_i32(<4 x i32> %s1) { +; CHECK-LABEL: vminv_s_v4i32_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: mvn r0, #-2147483648 +; CHECK-NEXT: vminv.s32 r0, q0 +; CHECK-NEXT: bx lr + %r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %s1) + ret i32 %r +} + +define arm_aapcs_vfpcc i8 @vminv_u_v16i8_i32(<16 x i8> %s1) { +; CHECK-LABEL: vminv_u_v16i8_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #255 +; CHECK-NEXT: vminv.u8 r0, q0 +; CHECK-NEXT: bx lr + %r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %s1) + ret i8 %r +} + +define arm_aapcs_vfpcc i16 @vminv_u_v8i16_i32(<8 x i16> %s1) { +; CHECK-LABEL: vminv_u_v8i16_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movw r0, #65535 +; CHECK-NEXT: vminv.u16 r0, q0 +; CHECK-NEXT: bx lr + %r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %s1) + ret i16 %r +} + +define arm_aapcs_vfpcc i32 @vminv_u_v4i32_i32(<4 x i32> %s1) { +; CHECK-LABEL: vminv_u_v4i32_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov.w r0, #-1 +; CHECK-NEXT: vminv.u32 r0, q0 +; CHECK-NEXT: bx lr + %r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %s1) + ret i32 %r +}