From: Petar Avramovic <Petar.Avramovic@rt-rk.com>
Date: Fri, 26 Jul 2019 13:08:06 +0000 (+0000)
Subject: [MIPS GlobalISel] Select inttoptr and ptrtoint
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=85b958de34549ace16684c3ec157f2e9153a08bb;p=llvm

[MIPS GlobalISel] Select inttoptr and ptrtoint

Select G_INTTOPTR and G_PTRTOINT for MIPS32.

Differential Revision: https://reviews.llvm.org/D65217


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367104 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsInstructionSelector.cpp b/lib/Target/Mips/MipsInstructionSelector.cpp
index 45a47ad3c08..102769895df 100644
--- a/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -265,6 +265,11 @@ bool MipsInstructionSelector::select(MachineInstr &I,
              .add(I.getOperand(2));
     break;
   }
+  case G_INTTOPTR:
+  case G_PTRTOINT: {
+    I.setDesc(TII.get(COPY));
+    return selectCopy(I, MRI);
+  }
   case G_FRAME_INDEX: {
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
              .add(I.getOperand(0))
diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index 4abc4b27bae..a62a077eba3 100644
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -89,9 +89,12 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
       .legalFor({s32})
       .clampScalar(0, s32, s32);
 
-  getActionDefinitionsBuilder(G_GEP)
+  getActionDefinitionsBuilder({G_GEP, G_INTTOPTR})
       .legalFor({{p0, s32}});
 
+  getActionDefinitionsBuilder(G_PTRTOINT)
+      .legalFor({{s32, p0}});
+
   getActionDefinitionsBuilder(G_FRAME_INDEX)
       .legalFor({p0});
 
diff --git a/lib/Target/Mips/MipsRegisterBankInfo.cpp b/lib/Target/Mips/MipsRegisterBankInfo.cpp
index d8bcf16afd5..dba866d781b 100644
--- a/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -388,6 +388,8 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case G_ZEXTLOAD:
   case G_SEXTLOAD:
   case G_GEP:
+  case G_INTTOPTR:
+  case G_PTRTOINT:
   case G_AND:
   case G_OR:
   case G_XOR:
diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
new file mode 100644
index 00000000000..2add4dc1c61
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @inttoptr() {entry: ret void}
+  define void @ptrtoint() {entry: ret void}
+
+...
+---
+name:            inttoptr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: inttoptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(p0) = G_INTTOPTR %0(s32)
+    $v0 = COPY %1(p0)
+    RetRA implicit $v0
+
+...
+---
+name:            ptrtoint
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptrtoint
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = G_PTRTOINT %0(p0)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+
diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir b/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
new file mode 100644
index 00000000000..5e1fcc8aa78
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @inttoptr() {entry: ret void}
+  define void @ptrtoint() {entry: ret void}
+
+...
+---
+name:            inttoptr
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: inttoptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
+    ; MIPS32: $v0 = COPY [[INTTOPTR]](p0)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(p0) = G_INTTOPTR %0(s32)
+    $v0 = COPY %1(p0)
+    RetRA implicit $v0
+
+...
+---
+name:            ptrtoint
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptrtoint
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+    ; MIPS32: $v0 = COPY [[PTRTOINT]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_PTRTOINT %0(p0)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/inttoptr_and_ptrtoint.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/inttoptr_and_ptrtoint.ll
new file mode 100644
index 00000000000..c27b5a939a4
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/inttoptr_and_ptrtoint.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i32* @inttoptr(i32 %a) {
+; MIPS32-LABEL: inttoptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    move $2, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = inttoptr i32 %a to i32*
+  ret i32* %0
+}
+
+define i32 @ptrtoint(i32* %a) {
+; MIPS32-LABEL: ptrtoint:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    move $2, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = ptrtoint i32* %a to i32
+  ret i32 %0
+}
diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
new file mode 100644
index 00000000000..42cd6122c11
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @inttoptr() {entry: ret void}
+  define void @ptrtoint() {entry: ret void}
+
+...
+---
+name:            inttoptr
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: inttoptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32)
+    ; MIPS32: $v0 = COPY [[INTTOPTR]](p0)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(p0) = G_INTTOPTR %0(s32)
+    $v0 = COPY %1(p0)
+    RetRA implicit $v0
+
+...
+---
+name:            ptrtoint
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptrtoint
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0)
+    ; MIPS32: $v0 = COPY [[PTRTOINT]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_PTRTOINT %0(p0)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...