From: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date: Thu, 6 Jun 2019 12:38:11 +0000 (+0000)
Subject: AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=85127da0817226f1b206a93df995238a59cf3ce8;p=llvm

AArch64] Handle ISD::LRINT and ISD::LLRINT for float16

This patch is a follow up for D62018 to add lrint/llrint
support for float16.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62863


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362700 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index dde05404365..9c19e3cdf51 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3168,6 +3168,14 @@ let Predicates = [HasFRInt3264] in {
   defm FRINT64X : FRIntNNT<0b11, "frint64x">;
 } // HasFRInt3264
 
+let Predicates = [HasFullFP16] in {
+  def : Pat<(i32 (lrint f16:$Rn)),
+            (FCVTZSUWHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
+  def : Pat<(i64 (lrint f16:$Rn)),
+            (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
+  def : Pat<(i64 (llrint f16:$Rn)),
+            (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
+}
 def : Pat<(i32 (lrint f32:$Rn)),
           (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
 def : Pat<(i32 (lrint f64:$Rn)),
diff --git a/test/CodeGen/AArch64/llrint-conv-fp16.ll b/test/CodeGen/AArch64/llrint-conv-fp16.ll
new file mode 100644
index 00000000000..366c337b59f
--- /dev/null
+++ b/test/CodeGen/AArch64/llrint-conv-fp16.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  x0, h0
+; CHECK:       ret
+define i16 @testmhhs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+  %conv = trunc i64 %0 to i16
+  ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  x0, h0
+; CHECK:       ret
+define i32 @testmhws(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  x0, h0
+; CHECK:       ret
+define i64 @testmhxs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.i64.f16(half) nounwind readnone
diff --git a/test/CodeGen/AArch64/lrint-conv-fp16-win.ll b/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
new file mode 100644
index 00000000000..ec9a8b2be87
--- /dev/null
+++ b/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  w0, h0
+; CHECK-NEXT:  ret
+define i16 @testmhhs(half %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+  %conv = trunc i32 %0 to i16
+  ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  w0, h0
+; CHECK-NEXT:  ret
+define i32 @testmhws(half %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+  ret i32 %0
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  w8, h0
+; CHECK-NEXT:  sxtw    x0, w8
+; CHECK-NEXT:  ret
+define i64 @testmhxs(half %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+declare i32 @llvm.lrint.i32.f16(half) nounwind readnone
diff --git a/test/CodeGen/AArch64/lrint-conv-fp16.ll b/test/CodeGen/AArch64/lrint-conv-fp16.ll
new file mode 100644
index 00000000000..d812e2f585b
--- /dev/null
+++ b/test/CodeGen/AArch64/lrint-conv-fp16.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  x0, h0
+; CHECK:       ret
+define i16 @testmhhs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
+  %conv = trunc i64 %0 to i16
+  ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  x0, h0
+; CHECK:       ret
+define i32 @testmhws(half %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK:       frintx  h0, h0
+; CHECK-NEXT:  fcvtzs  x0, h0
+; CHECK:       ret
+define i64 @testmhxs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f16(half) nounwind readnone