From: Ivan Grokhotkov <ivan@espressif.com>
Date: Sun, 12 Aug 2018 22:10:29 +0000 (+0300)
Subject: soc/rtc: add support for external 32k oscillator
X-Git-Tag: v3.2-beta1~285^2~2
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=8365f0f5d2d82413d3fa40bfded3942499243fd1;p=esp-idf

soc/rtc: add support for external 32k oscillator

Compared to external 32k XTAL, when active oscillator is used as input,
some parameters need to be set differently.
---

diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h
index b02d31eac3..a528bdd15d 100644
--- a/components/soc/esp32/include/soc/rtc.h
+++ b/components/soc/esp32/include/soc/rtc.h
@@ -193,6 +193,11 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
  */
 void rtc_clk_32k_enable(bool en);
 
+/**
+ * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
+ */
+void rtc_clk_32k_enable_external();
+
 /**
  * @brief Get the state of 32k XTAL oscillator
  * @return true if 32k XTAL oscillator has been enabled
diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 38737fbaa2..30f20e0eb0 100644
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -62,6 +62,10 @@
 #define XTAL_32K_BOOTSTRAP_DBIAS_VAL    0
 #define XTAL_32K_BOOTSTRAP_TIME_US      7
 
+#define XTAL_32K_EXT_DAC_VAL    2
+#define XTAL_32K_EXT_DRES_VAL   3
+#define XTAL_32K_EXT_DBIAS_VAL  1
+
 /* Delays for various clock sources to be enabled/switched.
  * All values are in microseconds.
  * TODO: some of these are excessive, and should be reduced.
@@ -98,7 +102,7 @@ static bool rtc_clk_cpu_freq_from_mhz_internal(int mhz, rtc_cpu_freq_t* out_val)
 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
 static int s_cur_pll_freq;
 
-static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
+static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
 {
     SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
     CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
@@ -113,12 +117,17 @@ static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
 void rtc_clk_32k_enable(bool enable)
 {
     if (enable) {
-        rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
+        rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
     } else {
         CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
     }
 }
 
+void rtc_clk_32k_enable_external()
+{
+    rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
+}
+
 /* Helping external 32kHz crystal to start up.
  * External crystal connected to outputs GPIO32 GPIO33.
  * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
@@ -150,7 +159,7 @@ void rtc_clk_32k_bootstrap(uint32_t cycle)
     SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
     ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
 
-    rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL,
+    rtc_clk_32k_enable_common(XTAL_32K_BOOTSTRAP_DAC_VAL,
             XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
 }