From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 16 Sep 2019 00:20:54 +0000 (+0000)
Subject: AMDGPU/GlobalISel: Fix VALU s16 fneg
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=832d1e1170e4d9660c0c784797530b0554f9aeda;p=llvm

AMDGPU/GlobalISel: Fix VALU s16 fneg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371948 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index a99977d72d9..52254750f60 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -1108,6 +1108,11 @@ def : GCNPat <
   (S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x00008000)))
 >;
 
+def : GCNPat <
+  (fneg (f16 VGPR_32:$src)),
+  (V_XOR_B32_e32 (S_MOV_B32 (i32 0x00008000)), VGPR_32:$src)
+>;
+
 def : GCNPat <
   (fabs (f16 SReg_32:$src)),
   (S_AND_B32 SReg_32:$src, (S_MOV_B32 (i32 0x00007fff)))
@@ -1118,6 +1123,11 @@ def : GCNPat <
   (S_OR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x00008000))) // Set sign bit
 >;
 
+def : GCNPat <
+  (fneg (fabs (f16 VGPR_32:$src))),
+  (V_OR_B32_e32 (S_MOV_B32 (i32 0x00008000)), VGPR_32:$src) // Set sign bit
+>;
+
 def : GCNPat <
   (fneg (v2f16 SReg_32:$src)),
   (S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000)))
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
index ed0109e1f5b..9395b0c8653 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
@@ -95,11 +95,10 @@ body: |
     liveins: $vgpr0
     ; GCN-LABEL: name: fneg_s16_vv
     ; GCN: liveins: $vgpr0
-    ; GCN: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; GCN: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
-    ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]]
-    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16)
-    ; GCN: $vgpr0 = COPY [[COPY1]](s32)
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
+    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
+    ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FNEG %1
@@ -349,12 +348,11 @@ body: |
     liveins: $vgpr0
     ; GCN-LABEL: name: fneg_fabs_s16_vv
     ; GCN: liveins: $vgpr0
-    ; GCN: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; GCN: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
-    ; GCN: [[FABS:%[0-9]+]]:vgpr(s16) = G_FABS [[TRUNC]]
-    ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FABS]]
-    ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0(s32) = COPY [[FNEG]](s16)
-    ; GCN: $vgpr0 = COPY [[COPY1]](s32)
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
+    ; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[V_OR_B32_e32_]]
+    ; GCN: $vgpr0 = COPY [[COPY1]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FABS %1