From: Evandro Menezes <e.menezes@samsung.com>
Date: Fri, 11 Jan 2019 22:39:47 +0000 (+0000)
Subject: [AArch64] Improve Exynos predicates
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=82647e1dc565f3ef6f07ec296e534358500f15fe;p=llvm

[AArch64] Improve Exynos predicates

Expand the predicate using shifted arithmetic and logic instructions to also
consider the respective not shifted instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350976 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64SchedPredExynos.td b/lib/Target/AArch64/AArch64SchedPredExynos.td
index 2044e30ec1c..48c54230e9d 100644
--- a/lib/Target/AArch64/AArch64SchedPredExynos.td
+++ b/lib/Target/AArch64/AArch64SchedPredExynos.td
@@ -48,7 +48,10 @@ def ExynosArithFn   : TIIPredicate<
                                                CheckExtBy3]>]>]>>>,
                            MCOpcodeSwitchCase<
                              IsArithShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
+                             MCReturnStatement<ExynosCheckShift>>,
+                           MCOpcodeSwitchCase<
+                             IsArithUnshiftOp.ValidOpcodes,
+                             MCReturnStatement<TruePred>>],
                           MCReturnStatement<FalsePred>>>;
 def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
 
@@ -58,7 +61,10 @@ def ExynosLogicFn   : TIIPredicate<
                         MCOpcodeSwitchStatement<
                           [MCOpcodeSwitchCase<
                              IsLogicShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
+                             MCReturnStatement<ExynosCheckShift>>,
+                           MCOpcodeSwitchCase<
+                             IsLogicUnshiftOp.ValidOpcodes,
+                             MCReturnStatement<TruePred>>],
                           MCReturnStatement<FalsePred>>>;
 def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
 
@@ -73,7 +79,10 @@ def ExynosLogicExFn   : TIIPredicate<
                                    [ExynosCheckShift,
                                     CheckAll<
                                      [CheckShiftLSL,
-                                      CheckShiftBy8]>]>>>],
+                                      CheckShiftBy8]>]>>>,
+                             MCOpcodeSwitchCase<
+                               IsLogicUnshiftOp.ValidOpcodes,
+                               MCReturnStatement<TruePred>>],
                             MCReturnStatement<FalsePred>>>;
 def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;